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| pci 6150bb data book
pci 6150bb data book version 2.11 february 2005 website : http://www.plxtech.com technical support : http://www.plxtech.com/support/ phone : 408 774-9060 800 759-3735 fax : 408 774-2169 ? 2005 plx technology, inc. all rights reserved. plx technology, inc., retains the right to make changes to this product at any time, without notice. products may have minor variations to this publication, known as errata. plx assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of plx products. this device is not designed, intended, authorized, or warranted to be suitable for use in medical or life-support applications, devices, or systems, or other critical applications. plx technology and the plx logo are registered trademarks and fastlane is a trademark of plx technology, inc. hypertransport is a trademark of the hypertransport technology consortium. other brands and names are the property of their respective owners. order number: pci 6150-sil-db-p1-2.11; former hint part number: hb4 printed in the usa, february 2005 pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. v contents figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii supplemental documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii data assignment conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xviii revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xviii feature summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1. company and product information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2. fastlane pci 6000 bridge series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2.1. pci 6150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.3. feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4. application?multiple device expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 2. functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1. general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2. write transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.3. read transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3. pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1. pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2. pull-up and pull-down resistor recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.1. pci bus interface pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.2. clock-related pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.3. reset pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.4. compactpci hot swap pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.5. jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.6. serial eeprom pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.7. miscellaneous pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.7.1. system voltage pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3. pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 4. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1. primary and secondary clock inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2. secondary clock outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.3. disabling unused secondary clock outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.3.1. secondary clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.4. frequency division options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.5. using an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.6. running secondary port faster than primary port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 contents pci 6150bb data book, version 2.11 vi ? 2005 plx technology, inc. all rights reserved. 5. reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1. 66 mhz operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2.1. primary reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.2. secondary reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.3. jtag reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.4. software resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.5. power management internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3. register initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3.1. default initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3.2. serial eeprom initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3.3. host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 6. registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1. pci configuration register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.1. pci type 1 header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.2. device-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.1.2.1. chip, diagnostic, and arbiter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.1.2.2. primary flow-through control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.1.2.3. timeout control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6.1.2.4. miscellaneous options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6.1.2.5. prefetch control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.1.2.6. internal arbiter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6.1.2.7. test and serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 6.1.2.8. primary system error event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 6.1.2.9. gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.1.2.10. secondary clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 6.1.2.11. primary system error status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 6.1.2.12. read-only register control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 6.1.2.13. power management capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 6.1.2.14. hot swap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 6.1.2.15. vpd capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 7. serial eeprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2. serial eeprom access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.3. serial eeprom autoload mode at reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.4. serial eeprom data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.4.1. serial eeprom address and corresponding pci 6150 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 8. pci bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1. transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2. single address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.3. dual address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.4. device select (devsel#) generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.5. data phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.5.1. posted write transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.5.2. memory write and invalidate transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.5.3. delayed write transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.5.4. write transaction address boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.5.5. buffering multiple write transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.5.6. read transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.5.7. prefetchable read transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.5.8. non-prefetchable read transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.5.9. read prefetch address boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 contents pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. vii 8.5.10. delayed read requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.5.11. delayed read completion with target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.5.12. delayed read completion on initiator bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.5.13. configuration transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.5.14. pci 6150 type 0 access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.5.15. type 1-to-type 0 translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.5.16. type 1-to-type 1 forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.5.17. special cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.6. transaction termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.1. pci 6150-initiated master termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.2. master abort received by pci 6150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.6.3. target termination received by pci 6150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.6.3.1. posted write target termination response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 8.6.3.2. delayed write target termination response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8.6.3.3. delayed read target termination response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8.6.4. pci 6150-initiated target termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8.6.4.1. target retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8.6.4.2. target disconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 8.6.4.3. target abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 9. address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2. address ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2.1. i/o address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2.1.1. i/o base and limit address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3. memory address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.3.1. memory-mapped i/o base and limit address registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.3.1.1. prefetchable memory base and limit address registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.4. isa mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.5. vga support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.5.1. vga mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.5.2. vga snoop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 10. transaction ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1. transactions governed by ordering rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2. general ordering guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.3. ordering rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.4. data synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 11. error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2. address parity errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.3. data parity errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.3.1. configuration write transactions to configuration space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.3.2. read transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.3.3. posted write transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.3.4. delayed write transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.4. data parity error reporting summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.5. system error (p_serr#) reporting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 contents pci 6150bb data book, version 2.11 viii ? 2005 plx technology, inc. all rights reserved. 12. exclusive access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1. concurrent locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2. acquiring exclusive access across pci 6150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.3. ending exclusive access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 13. pci bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2. primary pci bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.3. secondary pci bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.3.1. secondary bus arbitration using internal arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.3.2. rotating-priority scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.3.3. fixed-priority scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.3.4. secondary bus arbitration using external arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.4. arbitration bus parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 14. gpio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1. gpio interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2. gpio serial stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.3. gpio control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 15. supported commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1. primary interface command set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.2. secondary interface command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 16. bridge behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1. bridge actions for various cycle types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.2. abnormal termination (master abort, initiated by bridge master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.3. parity and error reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 17. pci flow-through optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2. precautions when using non-optimized pci master devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.3. posted write flow through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.4. delayed read flow through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.5. read cycle optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.5.1. primary and secondary initial prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.5.2. primary and secondary incremental prefetch count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.5.3. primary and secondary maximum prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.6. read prefetch boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 18. power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.2. power management transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 19. hot swap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.2. led on/off (pi=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.3. hot swap signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.4. hot swap register control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.5. device hiding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 contents pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. ix 20. vpd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 21. testability/debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1. jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.1. ieee 1149.1 test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.2. jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.3. jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.1.4. jtag reset input trst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 22. mechanical specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1. 208-pin pqfp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.1.1. mechanical dimensions?208-pin pqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.1.2. physical layout with pinout?208-pin pqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.2. 256-pin pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.2.1. mechanical dimensions?256-pin pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.2.2. physical layout with pinout?256-pin pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 23. electrical specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1. general electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.2. pci signal timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 a. using pci 6150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 b. general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 b.1. hint/plx part number conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 b.2. package ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 b.3. united states and international representatives, and distributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 b.4. technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 c. pci 6150bb and pci 6350aa pin comparisons and signal differences . . . . . . . . . . . . . . . . c-1 c.1. pin assignment comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 c.2. package signal differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-2 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . index-1 pci 6150bb data book, version 2.11 x ? 2005 plx technology, inc. all rights reserved. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. xi figures pci 6150 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx 1-1. fastlane pci 6000 bridge series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1-2. pci 6150 pci-to-pci bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1-3. multiple device expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 3-1. worst-case power dissipation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 4-1. gpio clock mask implementation on system board example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4-2. clock mask and load shift timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 7-1. serial eeprom data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 13-1. secondary bus arbiter example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 19-1. hot insertion power-up sequence recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19- 1 22-1. pci 6150 mechanical dimensions?208-pin pqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22-2. pci 6150 top view?208-pin pqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22-3. pci 6150 mechanical dimensions?256-pin pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22-4. pci 6150 top view?256-pin pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 23-1. pci signal timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 pci 6150bb data book, version 2.11 xii ? 2005 plx technology, inc. all rights reserved. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. xiii tables 1-1. fastlane pci 6000 series pci and pci-x bridge product comparison . . . . . . . . . . . . . . . . . . . . . . . . 1-2 3-1. pin type abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2. generic pci bus interface pins that follow pci r2.3 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-3. clock pin pull-up/pull-down resistor requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-4. primary pci bus interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-5. secondary pci bus interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3-6. clock-related pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3-7. reset pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3-8. compactpci hot swap pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-9. eject_en# and gpio3fn# settings for enabling hot swap capability . . . . . . . . . . . . . . . . . . . . . . 3-14 3-10. jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3-11. serial eeprom pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3-12. miscellaneous pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3-13. power, ground, and reserved pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 4-1. gpio shift register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4-2. gpio serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4-3. pci clock frequency division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 5-1. reset input sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 6-1. pci configuration register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 7-1. serial eeprom address and corresponding pci 6150 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 8-1. pci transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-2. write transaction forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8-3. write transaction disconnect address boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8-4. read transaction prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8-5. read prefetch address boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8-6. device number to idsel s_ad pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8-7. p_serr# assertion requirements in response to master abort on posted write . . . . . . . . . . . . . . . 8-13 8-8. response to posted write target termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 8-9. p_serr# assertion requirements in response to posted write parity error . . . . . . . . . . . . . . . . . . 8-14 8-10. response to delayed write target termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8-11. p_serr# assertion requirements in response to delayed write . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8-12. response to delayed read target termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-16 8-13. p_serr# assertion requirements in response to delayed read . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 10-1. transaction ordering summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 11-1. primary interface parity error detect ed bit status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11-2. secondary interface parity error detected bit status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11-3. primary interface data parity error detected bit status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11-4. secondary interface data parity error detected bit status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11-5. p_perr# assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11-6. s_perr# assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11-7. p_serr# or s_serr# for data parity error assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 1 14-1. gpio pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 tables pci 6150bb data book, version 2.11 xiv ? 2005 plx technology, inc. all rights reserved. 15-1. primary interface supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15-2. secondary interface supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 16-1. bridge actions for various cycle types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 17-1. reprogramming prefetch registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 18-1. states and related actions during power management transitions . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 19-1. eject_en# and gpio3fn# settings for enabling hot swap capability . . . . . . . . . . . . . . . . . . . . . 19-1 21-1. jtag instructions (ieee standard 1149.1-1990) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 22-1. pci 6150 mechanical dimensions for figure 22-1 symbols (in millimeters)?208-pin pqfp . . . . . . 22-3 23-1. maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23-2. functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23-3. dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23-4. 66 mhz pci signal timing for figure 23-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 b-1. hint/plx part number conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .b-1 b-2. available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .b-2 c-1. pci 6150bb versus pci 6350aa pin assignment comparison?pqfp package . . . . . . . . . . . . . . . . .c-1 c-2. pci 6150bb versus pci 6350aa pin assignment comparison?pbga package . . . . . . . . . . . . . . . .c-1 c-3. signal differences between pci 6150bb and pci 6350aa pqfp and pbga packages . . . . . . . . . . .c-2 pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. xv registers 6-1. (pciidr; pci:00h) pci configuration id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6-2. (pcicr; pci:04h) primary pci command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6-3. (pcisr; pci:06h) primary pci status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6-4. (pcirev; pci:08h) pci revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6-5. (pciccr; pci:09h ? 0bh) pci class code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6-6. (pciclsr; pci:0ch) pci cache line size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6-7. (pciltr; pci:0dh) primary pci bus latency timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6-8. (pcihtr; pci:0eh) pci header type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6-9. (pcibistr; pci:0fh) pci built-in self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6-10. (pcipbno; pci:18h) pci primary bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6-11. (pcisbno; pci:19h) pci secondary bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6-12. (pcisubno; pci:1ah) pci subordinate bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 8 6-13. (pcisltr; pci:1bh) secondary pci bus latency timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 8 6-14. (pciiobar; pci:1ch) i/o base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6-15. (pciiolmt; pci:1dh) i/o limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6-16. (pcissr; pci:1eh) secondary pci status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6-17. (pcimbar; pci:20h) memory base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6-18. (pcimlmt; pci:22h) memory limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6-19. (pcipmbar; pci:24h) prefetchable memory base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 12 6-20. (pcipmlmt; pci:26h) prefetchable memory limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6-21. (pcipmbaru32; pci:28h) prefetchable memory base upper 32 bits. . . . . . . . . . . . . . . . . . . . . . . 6-13 6-22. (pcipmlmtu32; pci:2ch) prefetchable memory limit upper 32 bits . . . . . . . . . . . . . . . . . . . . . . . 6-13 6-23. (pciiobaru16; pci:30h) i/o base upper 16 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6-24. (pciiolmtu16; pci:32h) i/o limit upper 16 bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6-25. (cap_ptr; pci:34h) new capability pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6-26. (pciipr; pci:3dh) pci interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6-27. (bcntrl; pci:3eh) bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6-28. (ccntrl; pci:40h) chip control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6-29. (dcntrl; pci:41h) diagnostic control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6-30. (acntrl; pci:42h) arbiter control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6-31. (pftcr; pci:44h) primary flow-through control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6-32. (tocntrl; pci:45h) timeout control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6-33. (mscopt; pci:46h) miscellaneous options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6-34. (pitlpcnt; pci:48h) primary initial prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6-35. (sitlpcnt; pci:49h) secondary initial prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -23 6-36. (pincpcnt; pci:4ah) primary incremental prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6-37. (sincpcnt; pci:4bh) secondary incremental prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6-38. (pmaxpcnt; pci:4ch) primary maximum prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 6-39. (smaxpcnt; pci:4dh) secondary maximum prefetch count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 6-40. (sftcr; pci:4eh) secondary flow-through control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 26 6-41. (iacntrl; pci:50h) internal arbiter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6-42. (test; pci:52h) test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 6-43. (eepcntrl; pci:54h) serial eeprom control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 6-44. (eepaddr; pci:55h) serial eeprom address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -30 registers pci 6150bb data book, version 2.11 xvi ? 2005 plx technology, inc. all rights reserved. 6-45. (eepdata; pci:56h) serial eeprom data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 6-46. (pserred; pci:64h) p_serr# event disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -31 6-47. (gpiood; pci:65h) gpio[3:0] output data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6-48. (gpiooe; pci:66h) gpio[3:0] output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6-49. (gpioid; pci:67h) gpio[3:0] input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6-50. (sclkcntrl; pci:68h) secondary clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -33 6-51. (pserrsr; pci:6ah) p_serr# status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 6-52. (rrc; pci:9ch) read-only register control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 6-53. (pmcapid; pci:dch) power management capability id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 6-54. (pmnext; pci:ddh) power management next capability pointer . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 6-55. (pmc; pci:deh) power management capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 6-56. (pmcsr; pci:e0h) power management control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 6-57. (pmcsr_bse; pci:e2h) pmcsr bridge supports extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 6-58. (pmcdata; pci:e3h) power management data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 38 6-59. (hs_cntl; pci:e4h) hot swap control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 6-60. (hs_next; pci:e5h) hot swap next capability pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 9 6-61. (hs_csr; pci:e6h) hot swap control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 6-62. (pvpdid; pci:e8h) vital product data capability id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 6-63. (pvpd_next; pci:e9h) vital product data next capability pointer . . . . . . . . . . . . . . . . . . . . . . . . 6-40 6-64. (pvpdad; pci:eah) vital product data address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 6-65. (pvpdata; pci:ech) vpd data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. xvii preface the information contained in this document is subject to change without notice. although an effort has been made maintain accurate information, there may be misleading or even incorrect statements made herein. supplemental documentation the following is a list of documentation to provide further details: pci local bus specification, revision 2.1 , june 1, 1995 pci special interest group (pci-sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 291-2569, fax: 503 297-1090, http://www.pcisig.com/home pci local bus specification, revision 2.3 pci special interest group (pci-sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 291-2569, fax: 503 297-1090, http://www.pcisig.com/home pci to pci bridge architecture specification , revision 1.1 pci special interest group (pci-sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 291-2569, fax: 503 297-1090, http://www.pcisig.com/home pci bus power management interface specification, revision 1.1 , june 30, 1997 pci special interest group (pci-sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 291-2569, fax: 503 297-1090, http://www.pcisig.com/home picmg 2.1, r2.0, compactpci hot swap specification, january 2001 pci industrial computer manufacturers group (picmg) c/o virtual inc., 401 edgewater place, suite 500, wakefield, ma 01880, usa tel: 781 246-9318, fax: 781 224-1239, http://www.picmg.org ieee standard 1149.1-1990, ieee standard test access port and boundary-scan architecture , 1990 the institute of electrical and electronics engineers, inc. 445 hoes lane, po box 1331, piscataway, nj 08855-1331, usa tel: 800 678-4333 (domestic only) or 732 981-0060, fax: 732 981-1721, http://www.ieee.org/portal/index.jsp note: in this data book, shortened titles are provided to the previous ly listed documents. the following table lists these abbreviati ons. supplemental documentation abbreviations abbreviation document pci r2.3 pci local bus specification, revision 2.3 p-to-p bridge r1.1 pci to pci bridge architecture specification, revision 1.1 pci power mgmt. r1.1 pci bus power management interface specification , revision 1.1 picmg 2.1 r2.0 picmg 2.1 r2.0 compactpci hot swap specification preface pci 6150bb data book, version 2.11 xviii ? 2005 plx technology, inc. all rights reserved. data assignment conventions revision history data assignment conventions data width pci 6150 convention 1 byte (8 bits) byte 2 bytes (16 bits) word 4 bytes (32 bits) dword/dword 8 bytes (64 bits) qword/qword date version comments 5/02 1.2 production release, silicon revision ba1. 6/02 1.21 added jtag external pull up/low resistor requirement. 8/02 1.22 updated dc characteristic table. 5/03 2.0 production release, silicon revision bb . this release reflects plx part numbering. added silicon revision bb to section 2. section 5, changed pin type in tables for p_serr#, s_serr#, s_req0#, s_gnt[8:1]#, s_m66en, s_clko[9:0], and s_rstout#. removed section 6.2, ?extended register map?. removed section 6.3.3, ?extended registers?. updated configuration map in section 6.1 to reflect deletion of extended registers. updated register deh, bits [15:11]. added three notes to table in section 14.5, ?frequency division options.? updated section 20.3.1, 24-3fh. 9/04 2.1 sampling release, silicon revision bc. general enhancements to text to plx standard. update signal names to standard plx signal names. removed references to non-transparent mode. included missing subsystem vendor and device id registers. 2/05 2.11 changed silicon revision from bc back to bb. updated to reflect pci bus power management interface specification , revision 1.1 compliance. removed ?address translation? from features section block diagram. changed pin name of pin_led to pin_led/eject. included eject switch-related information to pin description. updated pin type column information in section 3 pin tables for eepclk, enum#, gpio3fn#, p_gnt#, p_idsel, pin_led/eject, p_lock#, p_m66en, p_req#, p_rstin#, p_serr#, s_gnt0#, s_gnt[8:1]#, s_rstout#, and s_serr#. changed bridge control register, bit 4 (bcntrl; pci:3eh) to reserved . removed subsystem vendor and device id registers, as they are not supported in this silicon revision. added lead-free rohs-compliant packaging information to section b.2, ?package ordering.? pci-to-pci bridge february 2005 high- performance , asynchronous 32-bit, 66 mhz pci-to-pci bridge version 2.11 for servers, storage, telecommunication, networking and embedded applications pci 6150 pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. xix feature summary feature summary the plx fastlane? pci 6150 32-bit, 66 mhz pci-to- pci bridge is designed for high-performance, programmable data rates and plls that can divide input clock frequencies up and down, which makes the device useful for bus expansion systems. the pci 6150 also has hot swap capability, which makes it useful in high-availability systems. in addition, the pci 6150 offers the largest data fifo among all 32-bit pci-to-pci bridges in today?s market, and sophisticated buffer management and configuration options, all of which are designed to customize performance optimization. the pci 6150 provides the following features and applications: pci r2.3 compliant 3.3v signaling, including 5v input signal tolerance and fast pci buffers provides 1 kb of buffering (data fifo) to maximize performance upstream and downstream posted write buffers (256 bytes each) upstream and downstream read data buffers (256 bytes each) supports up to four simultaneous posted write transactions and four simultaneous delayed transactions in each direction programmable prefetch of up to 256 bytes for maximum read performance optimization flow-through zero wait state burst up to 4 kb for large volume data transfer optional flow-through enable allows for customization fast back-to-back enable?read-only supported asynchronous design supports standard 66-to- 33 mhz and faster secondary port speed, such as 33-to-66 mhz conversion out-of-order delayed transactions enhanced address decoding 32-bit i/o address range 32-bit memory-mapped i/o address range isa aware mode for legacy support in the first 64 kb of i/o address range vga addressing and palette snooping support address stepping hardcoded to two clocks ten secondary clock outputs with pin-controlled enable and individual maskable control to nine bus masters on secondary interface support external arbiter or programmable arbitration for up to nine bus masters on secondary interface support hot swap ready picmg 2.1 r2.0 with pi=1 support for device hiding, eliminating mid-transaction extraction problems pci mobile design guide and power management d 3cold wakeup capable with pme# support four gpio pins with output control and power-up status latch capable serial eeprom loadable and programmable pci read-only register configurations serial eeprom load modification and recheck vpd support ieee standard 1149.1-1990 jtag interface for boundary scan test multiple ids check all device and revision ids industry-standard 208-pin plastic quad flat pack (pqfp) or 256-pin (ball) plastic ball grid array (pbga) package feature summary pci 6150bb data book, version 2.11 xx ? 2005 plx technology, inc. all rights reserved. pci 6150 block diagram primary bus secondary bus 4-entry write buffer (256 bytes) 4-entry read buffer (256 bytes) 4-entry read buffer (256 bytes) 4-entry write buffer (256 bytes) gpio serial eeprom clock buffers pci arbiter hot swap system detect pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 1-1 1?introduction 1 introduction this section provides information about plx technology, inc., and its products, the fastlane? pci 6000 bridge series, and pci 6150 features and applications. 1.1 company and product information plx technology, inc., is the leading supplier of standard interconnect silicon to the storage, communications, server, and embedded-control industries. plx?s comprehensive i/o interconnect product offering ranges from i/o accelerators, pci-to-pci bridges, pci-x-to-pci-x bridges, and hypertransport? bridges to the plx pci express-based family of switches and bridges currently under development. in addition to a broad product offering, plx provides development tool support through software development kits (sdks), hardware rapid development kits (rdks), and third-party tool support through the plx partner program. our complete tool offering, combined with leadership plx silicon, enables system designers to maximize system throughput, lower development costs, minimize system design risk, and provide faster time to market. the plx commitment to meeting customer requirements extends beyond complete product solutions, and includes active participation in industry associations. plx contributes to the key standard-setting bodies in our industry, including pci-sig? (the special interest group responsible for the creation and release of all pci specifications), picmg ? (the organization responsible for the new advancedtca? standard for fabrics), hypertransport? consortium, and blade systems alliance (blades). furthermore, plx is a key developer for pci express technology and a member of the intel ? developers network for pci express technology. founded in 1986, plx has been developing products based on the pci industry standard since 1994. plx is publicly traded (nasdaq:plxt) and headquartered in sunnyvale, ca, usa, with other domestic offices in utah and southern california. plx european operations are based in the united kingdom and asian operations are based in china and japan. 1.2 fastlane pci 6000 bridge series the plx fastlane pci 6000 series offers the industry?s broadest set of pci-to-pci and pci-x-to- pci-x bridges. these bridges allow additional devices to be attached to the pci bus, and provide the ability to include intelligent adapters on a pci bus. in addition, these bridges allow pci buses of different speeds to be part of the same subsystem. (refer to table 1-1 and figure 1-1.) the plx pci and pci-x family of interconnect products include both pci-to-pci and pci-x-to-pci-x bridging devices, offering system designers innovative features along with improved i/o performance. the plx fastlane pci 6000 series of pci-to-pci bridging products provide support for the entire range of current pci bus data widths and speeds, including 32-bit 33 mhz, 64-bit 66 mhz, and the latest 64-bit 133 mhz pci-x variety of the standard. the fastlane pci 6000 product line is distinguished by featuring the widest range of options, lowest power requirements, highest performance, and smallest footprint in the industry. the product line includes features such as the ability to clock the pci bus segments asynchronously to one another. the entire line of plx bridging products are designed to provide high-performance interconnect for servers, storage, telecommunications, networking, and embedded applications. like all plx interconnect chips, the fastlane pci 6000 series products are supported by plx comprehensive reference design tools and the industry-recognized plx support infrastructure. section 1 introduction fastlane pci 6000 bridge series pci 6150bb data book, version 2.11 1-2 ? 2005 plx technology, inc. all rights reserved. table 1-1. fastlane pci 6000 series pci and pci-x bridge product comparison features pci 6140-aa33pc pci 6150-bb66bc pci 6150-bb66pc pci 6152-cc33bc pci 6152-cc33pc pci 6152-cc66bc pci 6156-da33pc pci bus type 32-bit 33 mhz pci 32-bit 66 mhz pci 32-bit 33 mhz pci 32-bit 66 mhz pci 32-bit 33 mhz pci pci local bus support r2.1 compliant r2.3 compliant r2.2 compliant r2.2 compliant r2.2 compliant 3.3 and 5v tolerant i/o yes yes yes yes yes asynchronous operation no 25 to 66 mhz no no no power dissipation 200 mw 1.8w 300 mw 300 mw 300 mw gpio interface no four gpio pins four gpio pins four gpio pins no transparency modes transparent only transparent only transparent only transpar ent only transparent only compactpci- compatible hot swap friendly r2.0 with pi=1 friendly friendly ? data fifo?1 kb??? number of bus masters on secondary bus up to 4 up to 9 up to 4 up to 4 up to 10 retry architecture standard standard performance- optimized performance- optimized performance- optimized programmable flow-through ?yes??? programmable prefetch not specified up to 4 kb n/a n/a n/a zero wait state burst up to 1 kb up to 1 kb up to 1 kb up to 1 kb up to 1 kb serial eeprom support ? yes yes yes yes vital product data registers ? yes yes yes yes d 3 wakeup power management yes yes yes yes yes secondary clock outputs yes yes yes yes yes jtag support ? ieee 1149.1 compliant ??? packaging pqfp-128 pbga-256 tiny bga-160 tiny bga-160 pqfp-208 pqfp-208 pqfp-160 package size 23 x 17 mm 17 x 17 mm 15 x 15 mm 15 x 15 mm 31 x 31 mm 31 x 31 mm 32 x 32 mm rapid development kit pci 6140rdk pci 6150rdk pci 6152rdk pci 6152rdk pci 6156rdk section 1 fastlane pci 6000 bridge series introduction pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 1-3 1?introduction features pci 6350-aa66pc pci 6154-bb66bc pci 6254-bb66bc pci 6520-xx pci 6540-xx pci bus type 32-bit 66 mhz pci 64-bit 66 mhz pci 64-bit 66 mhz 64-bit 133 mhz pci-x 64-bit 133 mhz pci-x pci local bus support r2.3 compliant r2.3 compliant r2.3 compliant r2.3 compliant r2.3 compliant 3.3 and 5v tolerant i/o yes yes yes yes yes asynchronous operation yes 25 to 66 mhz 25 to 66 mhz 33 to 133 mhz 25 to 133 mhz power dissipation 1.47w 2.0w 2.0w 1.0w 1.0w gpio interface four gpio pins four gpio pins 16 gpio pins 8 gpio pins 16 gpio pins transparency modes transparent only transparent only transparent, non-transparent and universal modes transparent only transparent, non-transparent and universal modes compactpci- compatible hot swap ? ? r2.0 with pi=1 ? r2.0 with pi=1 data fifo 192 byte 1 kb 1 kb 10 kb 10 kb number of bus masters on secondary bus up to 9 up to 9 up to 9 up to 8 up to 8 retry architecture standard standard standard standard standard programmable flow-through yes yes yes yes yes programmable prefetch up to 2 kb up to 4 kb up to 4 kb up to 4 kb up to 4 kb zero wait state burst up to 4 kb up to 1 kb up to 1 kb up to 4 kb up to 4 kb serial eeprom support yes yes yes yes yes vital product data registers yes yes yes yes yes d 3 wakeup power management yes yes yes yes yes secondary clock outputs yes yes yes yes yes jtag support ieee 1149.1 compliant ieee 1149.1 compliant ieee 1149.1 compliant ieee 1149.1 compliant ieee 1149.1 compliant packaging pbga-256 pbga-304 pbga-365 pbga-380 pbga-380 pqfp-208 package size 17 x 17 mm 31 x 31 mm 31 x 31 mm 27 x 27 mm 27 x 27 mm 31 x 31 mm rapid development kit pci 6350rdk pci 6154rdk pci 6254rdk pci 6520rdk pci 6540rdk table 1-1. fastlane pci 6000 series pci and pci-x bridge product comparison (continued) section 1 introduction fastlane pci 6000 bridge series pci 6150bb data book, version 2.11 1-4 ? 2005 plx technology, inc. all rights reserved. figure 1-1. fastlane pci 6000 bridge series pci 6140 32-bit 33 mhz pqfp 133 mhz 33 mhz 66 mhz pci 6520 trans pci 6540 non-trans 32-bit 66 mhz pbga pci 6150 32-bit 33/66 mhz tinybga pci 6152 32-bit 66 mhz pqfp pci 6350 pci 6254 64-bit 66 mhz non-trans pci 6154 64-bit 66 mhz trans a s y n c h r o n o u s pci 6156 32-bit 33 mhz for dvr 10 masters section 1 feature description introduction pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 1-5 1?introduction 1.2.1 pci 6150 the pci 6150 is the most powerful pci-to-pci bridging device offered in the industry. as illustrated in figure 1-2, the pci 6150 is a two-port device providing a synchronous operation between the primary and secondary ports. figure 1-2. pci 6150 pci-to-pci bridge 1.3 feature description the pci 6150 is built upon the powerful plx pci-to- pci bridge architecture, and offers the largest data fifo among all 32-bit pci-to-pci bridges in today?s market. the pci 6150 provides the following features and applications: pci r2.3 compliant 3.3v signaling, including 5v input signal tolerance and fast pci buffers provides 1 kb of buffering (data fifo) to maximize performance upstream and downstream posted write buffers (256 bytes each) upstream and downstream read data buffers (256 bytes each) supports up to four simultaneous posted write transactions and four simultaneous delayed transactions in each direction programmable prefetch of up to 256 bytes for maximum read performance optimization flow-through zero wait state burst up to 4 kb for large volume data transfer optional flow-through enable allows for customization fast back-to-back enable?read-only supported asynchronous design supports standard 66-to- 33 mhz and faster secondary port speed, such as 33-to-66 mhz conversion out-of-order delayed transactions enhanced address decoding 32-bit i/o address range 32-bit memory-mapped i/o address range isa aware mode for legacy support in the first 64 kb of i/o address range vga addressing and palette snooping support address stepping hardcoded to two clocks ten secondary clock outputs with pin-controlled enable and individual maskable control to nine bus masters on secondary interface support external arbiter or programmable arbitration for up to nine bus masters on secondary interface support hot swap ready picmg 2.1 r2.0 with pi=1 support for device hiding, eliminating mid-transaction extraction problems pci mobile design guide and power management d 3cold wakeup capable with pme# support four gpio pins with output control and power-up status latch capable serial eeprom loadable and programmable pci read-only register configurations serial eeprom load modification and recheck vpd support ieee standard 1149.1-1990 jtag interface for boundary scan test multiple ids check all device and revision ids industry-standard 208-pin plastic quad flat pack (pqfp) or 256-pin (ball) plastic ball grid array (pbga) package pci 6150 asynchronous transparent pci power management support 9 bus master support 4 gpios hot swap support serial eeprom s upport 10 external clock buffers 32-bit, 66 mhz primary pci bus 32-bit, 66 mhz secondary pci bus section 1 introduction application?multiple device expansion pci 6150bb data book, version 2.11 1-6 ? 2005 plx technology, inc. all rights reserved. 1.4 application?multiple device expansion figure 1-3 illustrates the pci 6150 being used to provide electrical isolation to the pci bus. this is necessary because pci slots restrict the number of loads that can be accommodated. the devices on the secondary port must be pci , and the bus must operate at 32-bit, up to 66 mhz. this configuration is a common mechanism for providing multiple pci devices on a single bus without exceeding the bus load limitation as defined in pci r2.3 . figure 1-3. multiple device expansion 32-bit, 66 mhz pci bus pci 6150 pci device pci device pci device pci device primary port secondary port pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 2-1 2?functional overview 2 functional overview this section describes general operation of the pci 6150 bridge, and provides an overview of write and read transactions. 2.1 general operation each pci port can run at different (asynchronous) frequencies, up to 66 mhz, which allows the designer to optimize the performance of each bus. the pci 6150 provides an internal arbiter function on the secondary bus, for up to nine secondary bus masters. however, the internal arbiter may be disabled if an external arbiter is used. the pci 6150 also sources ten secondary pci clock outputs. the pci 6150 supports a serial eeprom device for register configuration data. this allows the pci 6150 to automatically load custom configuration upon power-up, which minimizes the software overhead of configuring the bridge through a host processor. the pci 6150 provides features satisfying the requirements of pci power mgmt. r1.1 , supporting power management states d 0 through d 3cold and d 3hot . (refer to section 18, ?power management,? for further details.) the pci 6150 is compactpci hot swap ready , and complies with picmg 2.1 r2.0 with high availability programming interface level 1 (pi=1). (refer to section 19, ?hot swap,? for further details.) the pci 6150 fully supports vital product data (vpd) by providing the address, data, and control registers (pvpdad; pci:eah, pvpdata; pci:ech, pvpdid; pci:e8h, and pvpd_next; pci:e9h) for accessing vpd stored in the unused portion of the serial eeprom. vpd allows reading or writing of user data to the upper 192 bytes of serial eeprom space, and that data can contain information such as board serial number, software revision, firmware revision, or other data required for non-volatile storage. (refer to section 20, ?vpd,? for further details.) 2.2 write transactions the primary or secondary bus accomplishes a write operation by placing the address and data into the write buffer . this initiates a pci write operation on the other bus. the write operation is called a posted write operation, because the initiating bus performs the write, then moves on without waiting for the operation to complete. in addition, the pci 6150 has the capability to start a write operation before receiving all write data. in this case, the write operation begins when there is sufficient write data to begin the burst, providing a flow-through operation as the balance of the write data arrives in the device. 2.3 read transactions when the downstream or upstream bus needs to read data from the other bus, the bus places the read request into the read command queue . this initiates a read operation on the other bus, and the data is placed into the associated read buffer as it returns. for pci transactions, there is an additional prefetch mechanism when returning the requested read data. in this mode, the pci 6150 can be programmed to prefetch up to 1 kb of data at a time. this data is stored in the read buffer and is not flushed until the buffer times out. if requested, prefetched data can be delivered to the pci bus without the normal read on the other bus. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 3-1 3?pin description 3 pin description this section describes the pci 6150 pins, including pin summary, pull-up and pull-down resistor recommendations, and pinout listings. note: in this data book, the pbga balls are also referred to as pins. 3.1 pin summary tables 3-4 through table 3-8 and table 3-10 through table 3-13 describe each pci 6150 pin: primary pci bus interface secondary pci bus interface clock-related reset compactpci hot swap jtag serial eeprom interface miscellaneous power, ground, and reserved for a visual view of the pci 6150 pinout, refer to section 22, ?mechanical specs.? table 3-1 lists abbreviations used in section 3 to represent various pin types. table 3-1. pin type abbreviations abbreviation pin type i cmos input (5v input tolerant, i/o v dd =3.3v). i/o cmos bi-directional input output (5v input tolerant, i/o v dd =3.3v). o cmos output. pci pci compliant. pd internally pulled down. pu internally pulled up. pi pci input (5v input tolerant, i/o v dd =3.3v). po pci output. psts pci sustained three-state output. active low signal which must be driven inactive for one cycle before being three-stated to ensure high performance on a shared signal line. pts pci three-state bi-directional (5v input tolerant, i/o v dd =3.3v). section 3 pin description pull-up and pull-down resistor recommendations pci 6150bb data book, version 2.11 3-2 ? 2005 plx technology, inc. all rights reserved. 3.2 pull-up and pull-down resistor recommendations pull-up and pull-down resistor values are not critical. with the exception of those mentioned in section 3.2.1, a 10k-ohm resistor is recommended unless stated otherwise. 3.2.1 pci bus interface pins the pins detailed in table 3-2 are generic primary and secondary pci interface pins. when producing motherboards, system slot cards, adapter cards, backplanes, and so forth, the termination of these pins should follow the guidelines detailed in pci r2.3 . the following guidelines are not exhaustive and should be read in conjunction with the appropriate sections of pci r2.3 . pci control signals require a pull-up resistor on the motherboard to ensure that these signals are always at valid values when a pci bus agent is not driving the bus. these control signals include devsel#, frame#, irdy#, lock#, perr#, serr#, stop#, and trdy#. the point-to-point and shared bus signals do not require pull-up resistors, as bus parking ensures that these signals remain stable. the value of these pull-up resistors depends on the bus loading. pci r2.3 provides formulas for calculating these resistors. when making adapter cards in which the pci 6150 primary port is wired to the pci connector, pull-up resistors are not required because they are pre-installed on the motherboard. based on the above, in an embedded design, pull-up resistors may be required for pci control signals on the primary and secondary buses. whereas, for a pci adapter card design, pull-up resistors are required only on the pci 6150 port that is not connected to the motherboard or host system. s_m66en must be pulled high or low with a 10k-ohm resistor. the s_req[8:1]# inputs must be pulled high with a 10k-ohm pull-up resistor to v dd . s_req0# also requires a 10k-ohm pull-up resistor to v dd if s_cfn#=0. pull s_gnt[8:1]# high if s_cfn#=1. 3.2.2 clock-related pins clock routing is detailed in section 4, ?clocking.? pull-up resistors are not required on the s_clko[9:0] pins; however, a series termination resistor is required when using these pins. s_clko0 may require a pull-up resistor when this pin is disabled (sclkcntrl[1:0]=11b; pci:68h). s_clko[9:0] may also require pull-up resistors if they are disabled by pulling msk_in high. table 3-3 delineates the remaining clock pin resistor requirements. notes: * refer also to the text preceding this table. ** msk_in is used in the pqfp package only. 3.2.3 reset pins the p_rstin# reset signal may require a pull-up resistor, depending on the application. the s_rstout# reset signal does not require a pull-up nor pull-down resistor. table 3-2. generic pci bus interface pins that follow pci r2.3 layout guidelines bus pin name primary p_ad[31:0], p_cbe[3:0]#, p_devsel#, p_frame#, p_gnt#, p_idsel, p_irdy#, p_lock#, p_m66en, p_par, p_perr#, p_req#, p_serr#, p_stop#, p_trdy# secondary s_ad[31:0], s_cbe[3:0]#, s_devsel#, s_frame#, s_gnt[8:0]#, s_irdy#, s_lock#, s_m66en, s_par, s_perr#, s_req[8:0]#, s_serr#, s_stop#, s_trdy# table 3-3. clock pin pull-up/pull-down resistor requirements resistor requirements pin name pull high or low if unused oscin optionally pull high or low msk_in**, oscsel# pull-up or pull-down resistor not required p_clkin, s_clkin, s_clko[9:0]* section 3 pull-up and pull-down resistor recommendations pin description pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 3-3 3?pin description 3.2.4 compactpci hot swap pins if hot swap is used, pull the eject_en# and gpio3fn# pins low. the gpio3 pin is then used as an eject input for hot swap. pin_led/eject is then connected to an external led. if eject_en# is not used, it must be at logic 0 and pulled low. if hot swap is not used, tie gpio3fn# high or gpio3 low. eject_en# is don?t care. 3.2.5 jtag pins the tck, tdi, and tms jtag signals must be pulled high or low to a known state, using an external resistor. trst# must be pulled low, using a 330-ohm resistor. the tdo signal does not require a pull-up nor pull-down resistor. 3.2.6 serial eeprom pins if a serial eeprom is used, ee_en# requires a pull-down resistor. if a serial eeprom is not used, pull up ee_en# to disable serial eeprom autoload during system boot-up. eepclk does not require a pull-up nor pull-down resistor. eepdata requires an external pull-up resistor. 3.2.7 miscellaneous pins the bpcc_en signal may optionally be pulled high or low. s_cfn# may also optionally be pulled high or low, but must be tied low to use the internal arbiter. when programmed as outputs, the gpio[3:0] pins do not require external pull-up nor pull-down resistors. if configured as inputs, pull the gpio[3:0] pins high or low, depending on the application. if hot swap is not used, tie gpio3fn# high or gpio3 low. when pulled high, cfg66 enables the pci 6150 to declare 66 mhz capability. 3.2.7.1 system voltage pins for designs and add-in cards that have an independent v io voltage source, and for which proper power sequencing cannot be guaranteed, the current between the v io voltage source and pci 6150 v io pins must be limited to protect the device from long-term undue stress resulting in damage ( such as from resistor insertion). note: by their nature, add-in cards cannot assume proper power sequencing and requirements must be met by system power supplies. use the following guidelines to determine the required resistance value for the p_v io and s_v io pins: 3.3v signaling environments ?40 to 200-ohm resistance between the v io voltage source and the pci 6150 v io pins is recommended if v io is a maximum of 3.6v 3.3 or 5v signaling environments ?40 to 70-ohm resistance is recommended a single resistor can be used if the v io pins are bused, or multiple parallel resistors can be used between the v io voltage source and v io pins. the resistor power dissipation rating depends upon the resistance size and signaling environment. for example, if a single 50-ohm resistor is used in a 5v signaling environment, the worst-case power dissipation would result in 480 mw. (refer to figure 3-1.) if four, 200-ohm resistors are used in parallel, each would be required to dissipate 120 mw. any resistance value within the recommended ranges prevents the device from being damaged, while providing sufficient clamping action to keep the input voltage (v in ) below its maximum rating. a resistance value at the lower end of the range is recommended to provide preferable clamping action, and a sufficient v in margin. 480 mw = (v v) / r (5.5v (maximum signal amplitude, plus 10%) ? 0.6v (1 diode drop)) 2 50 ohms figure 3-1. worst-case power dissipation example section 3 pin description pinout pci 6150bb data book, version 2.11 3-4 ? 2005 plx technology, inc. all rights reserved. 3.3 pinout note: refer to section 3.2 for pull-up and pull-down resistor recommendations not specifically stated in these tables. table 3-4. primary pci bus interface pins symbol signal name total pins pin type pqfp pin number pbga pin number function p_ad[31:0] primary address and data 32 i/o pts pci 49, 50, 55, 57, 58, 60, 61, 63, 67, 68, 70, 71, 73, 74, 76, 77, 93, 95, 96, 98, 99, 101, 107, 109, 112, 113, 115, 116, 118, 119, 121, 122 n3, t2, t4, n5, p5, t5, n6, r5, t6, p7, t7, r7, t8, p8, r8, t9, r12, p12, t14, r13, n12, t15, p16, n15, m14, m13, m15, l13, m16, l14, l15, l16 multiplexed address and data bus. address is indicated by p_frame# assertion during pci transactions. write data is stable and valid when p_irdy# is asserted and read data is stable and valid when p_trdy# is asserted. data is transferred on rising clock edges when p_irdy# and p_trdy# are asserted. during bus idle, the pci 6150 drives p_ad[31:0] to valid logic levels when p_gnt# is asserted. (refer to section 13, ?pci bus arbitration,? for further details.) p_cbe[3:0]# primary command and byte enables 4 i/o pts pci 64, 79, 92, 110 r6, r9, t13, n16 multiplexed command and byte enable fields. provides the transaction type during the pci address phase. in the data phase of pci memory write transactions, p_cbe[3:0]# provide byte enables. during bus idle, the pci 6150 drives p_cbe[3:0]# to valid logic levels when p_gnt# is asserted. (refer to section 13, ?pci bus arbitration,? for further details.) p_devsel# primary device select 1 i/o psts pci 84 p10 asserted by the target, indicating that the device is accepting the transaction. as a master, the pci 6150 waits for p_devsel# assertion within five cycles of p_frame# assertion; otherwise, the transaction terminates with a master abort. before being placed into a high- impedance state, p_devsel# is driven to a high state for one cycle. p_frame# primary frame 1 i/o psts pci 80 p9 driven by the initiator of a transaction to indicate the beginning and duration of an access. p_frame# de-assertion indicates the final data phase requested by the initiator. before being placed into a high-impedance state, p_frame# is driven to a high state for one cycle. p_gnt# primary grant 1 i pi 46 r1 when asserted, the pci 6150 can access the primary bus. during bus idle with p_gnt# asserted, the pci 6150 drives p_ad[31:0], p_cbe[3:0]#, and p_par to valid logic levels. (refer to section 13, ?pci bus arbitration,? for further details.) section 3 pinout pin description pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 3-5 3?pin description p_idsel primary initialization device select 1 i pi 65 p6 used as a chip select line for type 0 configuration accesses to pci 6150 configuration space. p_irdy# primary initiator ready 1 i/o psts pci 82 t10 driven by the initiator of a transaction to indicate its ability to complete the current data phase on the primary bus. once asserted in a data phase, p_irdy# is not de-asserted until the end of the data phase. before being placed into a high-impedance state, p_irdy# is driven to a de-asserted state for one cycle. p_lock# primary lock 1 i/o psts 87 r11 asserted by the bus master, indicating an atomic operation that may require multiple transactions to complete. primary lock asserted by master for multiple transactions to complete. if lock function is not needed, when no secondary pci devices support lock, pull high and do not connect to the pci bus. can be disabled by setting mscopt[13]=0; pci:46h. p_m66en primary 66 mhz enable 1 i pi 102 r14 set high to allow 66 mhz primary bus operation. along with s_m66en, controls the frequency output to the s_clko[9:0] pins. (refer to section 4, ?clocking,? for further details.) p_par primary parity 1 i/o pts pci 90 n11 parity is even across p_ad[31:0], p_cbe[3:0]#, and p_par [ that is, an even number of ones (1)]. p_par is an input, and is valid and stable for one cycle after the address phase (indicated by p_frame# assertion) for address parity. for write data phases, p_par is an input and valid one clock after p_irdy# assertion. for read data phases, p_par is an output and valid one clock after p_trdy# assertion. p_par is placed into a high-impedance state one cycle after the p_ad[31:0] lines are placed in to a high-impedance state. during bus idle, the pci 6150 drives p_par to a valid logic level when p_gnt# is asserted. p_perr# primary parity error 1 i/o psts pci 88 t12 asserted when a data parity error is detected for data received on the primary interface. before being placed into a high-impedance state, p_perr# is driven to a de-asserted state for one cycle. table 3-4. primary pci bus interface pins (continued) symbol signal name total pins pin type pqfp pin number pbga pin number function section 3 pin description pinout pci 6150bb data book, version 2.11 3-6 ? 2005 plx technology, inc. all rights reserved. p_req# primary request 1 o po 47 p2 asserted by the pci 6150 to request ownership of the primary bus to perform a transaction. the pci 6150 de-asserts p_req# for at least two pci clock cycles before re-asserting it. (refer to section 13.2, ?primary pci bus arbitration,? for further details.) p_serr# primary system error 1 i/o pts 89 p11 p_serr# can be driven low by any device to indicate a system error condition. the pci 6150 drives p_serr# if one of the following conditions is met: address parity error posted write data parity error on target bus s_serr# is asserted master abort during posted write transaction target abort during posted write transaction posted write transaction discarded delayed write request discarded delayed read request discarded delayed transaction master timeout pull-up p_serr# through an external resistor. p_stop# primary stop 1 i/o psts pci 85 t11 asserted by the target to end the transaction on the current data phase. before being placed into a high- impedance state, p_stop# is driven to a de-asserted state for one cycle. p_trdy# primary target ready 1 i/o psts pci 83 r10 driven by the target of a transaction to indicate its ability to complete the current data phase on the primary bus. before being placed into a high- impedance state, p_trdy# is driven to a de-asserted state for one cycle. total 49 table 3-4. primary pci bus interface pins (continued) symbol signal name total pins pin type pqfp pin number pbga pin number function section 3 pinout pin description pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 3-7 3?pin description table 3-5. secondary pci bus interface pins symbol signal name total pins pin type pqfp pin number pbga pin number function s_ad[31:0] secondary address and data 32 i/o pts pci 206, 204, 203, 201, 200, 198, 197, 195, 192, 191, 189, 188, 186, 185, 183, 182, 165, 164, 162, 161, 159, 154, 152, 150, 147, 146, 144, 143, 141, 140, 138, 137 a4, d5, c5, a5, b5, d6, a6, c6, c7, a7, b7, c8, a8, b8, a9, c9, c12, d12, a14, b13, a15, b16, e13, c16, e14, d16, f13, e16, f14, f15, f16, g16 multiplexed address and data bus. address is indicated by s_frame# assertion during pci transactions. write data is stable and valid when s_irdy# is asserted and read data is stable and valid when s_trdy# is asserted. data is transferred on rising clock edges when s_irdy# and s_trdy# are asserted. during bus idle, the pci 6150 drives s_ad[31:0] to valid logic levels when s_gnt[8:0]# are not asserted. (refer to section 13, ?pci bus arbitration,? for further details.) s_cbe[3:0]# secondary command and byte enables 4 i/o pts pci 194, 180, 167, 149 b6, b9, b12, e15 multiplexed command and byte enable fields. provides the transaction type during the pci address phase. in the data phase of pci memory write transactions, s_cbe[3:0]# provide the byte enables. during bus idle, pci 6150 drives s_cbe[3:0]# to valid logic levels when s_gnt[8:0]# are not asserted when external arbitration is not activated. (refer to section 13, ?pci bus arbitration,? for further details.) s_devsel# secondary device select 1 i/o psts pci 175 a11 asserted by the target, indicating that the device is accepting the transaction. as a master, the pci 6150 waits for s_devsel# assertion within five cycles of s_frame# assertion; otherwise, the transaction terminates with a master abort. before being placed into a high- impedance state, s_devsel# is driven to a high state for one cycle. s_frame# secondary frame 1 i/o psts pci 179 a10 driven by the initiator of a transaction to indicate the beginning and duration of an access. s_frame# de-assertion indicates the final data phase requested by the initiator. before being placed into a high-impedance state, s_frame# is driven to a high state for one cycle. s_gnt0# secondary grant 0 1 i/o pts 10 d1 behaves as s_gnt[8:1]# when external arbitration is not activated. when external arbitration is activated, becomes the external bus request output from the pci 6150. section 3 pin description pinout pci 6150bb data book, version 2.11 3-8 ? 2005 plx technology, inc. all rights reserved. s_gnt[8:1]# secondary grants 8 through 1 8 o po 19, 18, 17, 16, 15, 14, 13, 11 g1, f1, f2, g3, f4, e1, e2, f3 asserted by the pci 6150 to access the secondary bus. the pci 6150 de-asserts s_gnt[8:1]# for at least two pci clock cycles before re-asserting them. during bus idle, with s_gnt[8:1]# asserted, the pci 6150 drives s_ad[31:0], s_cbe[3:0]#, and s_par to valid logic levels. (refer to section 13, ?pci bus arbitration,? for further details.) pull s_gnt[8:1]# high if s_cfn#=1. s_irdy# secondary initiator ready 1 i/o psts pci 177 b10 driven by the initiator of a transaction to indicate its ability to complete the current data phase on the secondary bus. once asserted in a data phase, it is not de-asserted until end of the data phase. before being placed into a high- impedance state, s_irdy# is driven to a de-asserted state for one cycle. s_lock# secondary lock 1 i/o psts 172 c11 asserted by the bus master, indicating an atomic operation that may require multiple transactions to complete. s_m66en secondary 66 mhz enable 1 i/o pts 153 d15 driven low if p_m66en is low; otherwise, driven from outside to select 66 or 33 mhz. s_m66en must be pulled high or low with a 10k-ohm resistor. along with p_m66en, controls the frequency output to the s_clko[9:0] pins. (refer to section 4, ?clocking,? for further details.) s_par secondary parity 1 i/o pts pci 168 a13 parity is even across s_ad[31:0], s_cbe[3:0]#, and s_par [ that is, an even number of ones (1)]. s_par is an input, and is valid and stable for one cycle after the address phase (indicated by s_frame# assertion) for address parity. for write data phases, s_par is an input and valid one clock after s_irdy# assertion. for read data phases, s_par is an output and valid one clock after s_trdy# assertion. s_par is placed into a high-impedance state one cycle after the s_ad[31:0] lines are placed in to a high-impedance state. during bus idle, the pci 6150 drives s_par to a valid logic level when s_gnt[8:1]# are asserted. (refer to section 13, ?pci bus arbitration,? for further details.) table 3-5. secondary pci bus interface pins (continued) symbol signal name total pins pin type pqfp pin number pbga pin number function section 3 pinout pin description pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 3-9 3?pin description s_perr# secondary parity error 1 i/o psts pci 171 a12 asserted when a data parity error is detected for data received on the secondary interface. before being placed into a high-impedance state, s_perr# is driven to a de-asserted state for one cycle. s_req0# secondary request 0 1 i/o pts 207 b4 asserted by an external device to request to start a transaction on the secondary bus. must be externally pulled up through resistors to v dd . when external arbitration is activated, becomes the external bus grant input from the pci 6150. s_req[8:1]# secondary requests 8 through 1 8 i pi 9, 8, 7, 6, 5, 4, 3, 2 e4, e3, d2, c1, c2, d3, a2, b3 asserted by an external device to request secondary bus ownership to perform a transaction. s_req[8:1]# must be externally pulled up through 10k-ohm resistors to v dd . s_serr# secondary system error 1 i/o pts 169 d11 s_serr# can be driven low by any device to indicate a system error condition. the pci 6150 drives s_serr# if the following conditions are met: address parity error posted write data parity error on target bus master abort during posted write transaction target abort during posted write transaction posted write transaction discarded delayed write request discarded delayed read request discarded delayed transaction master timeout pull-up s_serr# through an external resistor. s_stop# secondary stop 1 i/o psts pci 173 b11 asserted by the secondary target to end the transaction on the current data phase. before being placed into a high- impedance state, s_stop# is driven to a de-asserted state for one cycle. table 3-5. secondary pci bus interface pins (continued) symbol signal name total pins pin type pqfp pin number pbga pin number function section 3 pin description pinout pci 6150bb data book, version 2.11 3-10 ? 2005 plx technology, inc. all rights reserved. s_trdy# secondary target ready 1 i/o psts pci 176 c10 driven by the target of a transaction to indicate its ability to complete the current data phase on the secondary bus. once asserted in a data phase, it is not de-asserted until end of the data phase. before being placed into a high- impedance state, s_trdy# is driven to a de-asserted state for one cycle. total 64 table 3-5. secondary pci bus interface pins (continued) symbol signal name total pins pin type pqfp pin number pbga pin number function section 3 pinout pin description pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 3-11 3?pin description table 3-6. clock-related pins symbol signal name total pins pin type pqfp pin number pbga pin number function msk_in secondary clock disable serial input pqfp: 1 pbga: 0 i 126 ? used by hardware mechanism to disable secondary clock outputs. the serial stream is received by msk_in, starting when p_rstin# is detected de-asserted and s_rstout# is detected asserted. the serial data is used for selectively disabling secondary clock outputs and is shifted into the secondary clock control configuration register (sclkcntrl; pci:68h). when tied low, enables all secondary clock outputs. tied high, the clocks become active until high after reset. after ones (1) shift in, the clocks are driven high. note: used in the pqfp package only. if using the pbga package, use software to disable unused secondary clock buffers through the sclkcntrl; pci:68h register. oscsel# external oscillator enable 1i 51 k16 enables external clock connection for the secondary interface. if low, the secondary bus clock outputs use the clock signal from oscin, instead of p_clkin, to generate s_clko[9:0]. may optionally be pulled high or low. if high, p_clkin is used. oscsel# must not remain unconnected. note: when oscsel# input is v dd , the external clock function is disabled and osc_in input is ignored, oscin external oscillator input 1i 54 k15 external clock input used to generate secondary output clocks when enabled through the oscsel# pin. pull high or low if unused. note: when oscsel# input is v dd , the external clock function is disabled and osc_in input is ignored, p_clkin primary clock input 1i 45 m4 provides timing for primary interface transactions. s_clkin secondary clock input 1i 21 h3 provides timing for secondary interface transactions. section 3 pin description pinout pci 6150bb data book, version 2.11 3-12 ? 2005 plx technology, inc. all rights reserved. s_clko[9:0] secondary clock output 10 o 42, 41, 39, 38, 36, 35, 33, 32, 30, 29 m3, m2, n1, l4, l3, m1, l2, l1, k3, k2 provides s_clkin or oscin (if enabled) phase synchronous output clocks. pull-up resistors are not required on s_clko[9:0]; however, a series termination resistor is required when using these pins. s_clko0 drives the compactpci backplane. total?pqfp total?pbga 15 14 table 3-6. clock-related pins (continued) symbol signal name total pins pin type pqfp pin number pbga pin number function section 3 pinout pin description pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 3-13 3?pin description table 3-7. reset pins symbol signal name total pins pin type pqfp pin number pbga pin number function p_rstin# primary reset input 1 i pi 43 p1 when p_rstin# is active, asynchronously place outputs in a high- impedance state, and float p_serr# and p_gnt#. all primary port pci standard configuration registers at offsets 00h to 3fh revert to their default state. when asserted, all primary pci signals are placed into a high-impedance state. may require a pull-up resistor, depending on the application. s_rstout# secondary reset output 1 o po 22 h1 asserted when one of the following conditions is met: p_rstin# is asserted s_rstout# remains asserted if p_rstin# is asserted and does not de-assert until p_rstin# is de-asserted. bridge control register secondary reset bit in configuration space is set (bcntrl[6]=1; pci:3eh). s_rstout# remains asserted until bcntrl[6]=0. when asserted, all control signals are placed into a high-impedance state and zeros (0) are driven on s_ad[31:0], s_cbe[3:0]# and s_par. total 2 section 3 pin description pinout pci 6150bb data book, version 2.11 3-14 ? 2005 plx technology, inc. all rights reserved. note: if the hot swap function is not used, pull gpio3fn# high or gpio3 low to disable the function. table 3-8. compactpci hot swap pins symbol signal name total pins pin type pqfp pin number pbga pin number function eject_en# ejector pin use enable 1 i 106 r16 used to enable the gpio3 pin as eject input. if this pin is 1, gpio3 functions as a gpio pin. gpio3 only functions as eject input when both gpio3fn# and eject_en# are tied low, which also enables hot swap capability. (refer to table 3-9.) if not used, eject_en# must be at logic 0 and pulled low. enum# enumeration 1 o od pts 127 j14 indicates an open-drain bused signal asserted when an adapter was inserted or is ready to be extracted from a pci slot. asserted through the hot swap registers (hs_cntl; pci:e4h, hs_csr; pci:e6h, and hs_next; pci:e5h). if used, enum# requires a pull-up resistor. gpio3fn# gpio3 function select 1 i pi 155 b14 when gpio3fn# is tied high, gpio3 functions as a gpio pin regardless of eject_en# state. gpio3 functions as ejector input only when both gpio3fn# and eject_en# are tied low (hot swap enabled). (refer to table 3-9.) pin_led/ eject status blue led 1 i/o 128 j16 active high signal that allows other circuits to drive the blue hot swap led. turns on led if rstin# is asserted, or when the loo bit is set (hs_csr[3]=1; pci:e6h) and rstin# is de-asserted. after rstin# de-assertion, the led remains on until the eject switch (handle) is closed, then the pci 6150 turns off the led. if used, pin_led/eject does not require a pull-up nor pull-down resistor. however, if unused, pin_led/eject must be pulled high. total 4 table 3-9. eject_en# and gpio3fn# settings for enabling hot swap capability eject_en# gpio3fn# hot swap eject input 0 0 enabled gpio3 don?t care 1 disabled ? section 3 pinout pin description pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 3-15 3?pin description note: the jtag interface is described in section 21, ?testability/debug.? table 3-10. jtag pins symbol signal name total pins pin type pqfp pin number pbga pin number function tck test clock input 1 i pu 133 h15 used to clock state information and test data into and out of the pci 6150 during test access port (tap) operation. pull tck high or low to a known state, using an external resistor. tdi test data input 1 i pu 129 j15 used to serially shift test data and test instructions into the pci 6150 during tap operation. pull tdi high or low to a known state, using an external resistor. tdo test data output 1 o 130 h16 used to serially shift test data and test instructions out of the pci 6150 during tap operation. pull tdo high using an external resistor. tms test mode select 1 i pu 132 h14 used to control the pci 6150 tap controller state. pull tms high or low to a known state, using an external resistor. trst# test reset 1 i 134 g15 asynchronous jtag logic reset. provides asynchronous initialization of the tap controller. trst# must be externally pulled low with a 330-ohm resistor. total 5 section 3 pin description pinout pci 6150bb data book, version 2.11 3-16 ? 2005 plx technology, inc. all rights reserved. note: when input to ee_en# is v dd , the serial eeprom function is disabled and the eepclk and eepdata pins are ignored. table 3-11. serial eeprom pins symbol signal name total pins pin type pqfp pin number pbga pin number function ee_en# serial eeprom enable 1 i 103 c15 to enable serial eeprom use, ee_en# should be 0. otherwise, connect to logic 1 state. if a serial eeprom is used, ee_en# requires a pull-down resistor. if a serial eeprom is not used, pull up ee_en# to disable serial eeprom autoload during system boot-up. eepclk serial eeprom clock 1 o 158 c14 clock signal to the serial eeprom interface. used during autoload and for vpd functions. eepclk is placed into a high-impedance state if ee_en#=1. eepdata serial eeprom data 1 i/o 160 d14 serial data interface to the serial eeprom. requires an external pull-up resistor. eepdata is placed into a high-impedance state if ee_en#=1. total 3 section 3 pinout pin description pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 3-17 3?pin description table 3-12. miscellaneous pins symbol signal name total pins pin type pqfp pin number pbga pin number function bpcc_en bus/power click control 1i 44 n2 when tied high and the pci 6150 is placed into the d 3hot power state, the pci 6150 places the secondary bus into the b 2 power state. the pci 6150 disables the secondary clocks and drives them to 0. when tied low, placing the pci 6150 into the d 3hot power state has no effect on the secondary bus clocks. cfg66 primary configuration 66 mhz pqfp: 1 pbga: 0 i125 ? pin state is reflected in the primary status register (pcisr[5]; pci:06h). when 1, cfg66 enables the pci 6150 to declare 66 mhz capability. otherwise, cfg66 has no effect on pci 6150 operation. note: used in the pqfp package only. in the pbga package, the 66 mhz-capable bits are hardwired to 1 (pcisr[5]=1; pci:06h and pcissr[5]=1; pci:1eh) to indicate 66 mhz capability. gpio[3:0] general purpose input/ output 3 to 0 4 i/o pu 24, 25, 27, 28 j3, j2, j1, k1 general purpose signals, programmable as input-only or bi-directional by writing to the gpio output enable register (gpiooe; pci:66h). during p_rstin# assertion, gpio[3:0] are used to shift in the clock disable serial data. if configured as input, pull high or low, depending on application. when hot swap is enabled, gpio3 functions as ejector input only when both gpio3fn# and eject_en# are tied low. p_v io primary interface i/o voltage 1i 124 k14 must be tied to 3.3 or 5v, depending on the primary interface signaling voltage. section 3 pin description pinout pci 6150bb data book, version 2.11 3-18 ? 2005 plx technology, inc. all rights reserved. s_cfn# internal arbiter enable 1i 23 h2 values: 0 = uses internal arbiter. 1 = uses external arbiter. may optionally be pulled high or low; however, s_cfn# must be tied low to use the internal arbiter. s_v io secondary interface i/o voltage 1i 135 g14 must be tied to 3.3 or 5v, depending on the secondary interface signaling voltage. total?pqfp total?pbga 9 8 table 3-12. miscellaneous pins (continued) symbol signal name total pins pin type pqfp pin number pbga pin number function section 3 pinout pin description pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 3-19 3?pin description table 3-13. power, ground, and reserved pins symbol signal name total pins pin type pqfp pin number pbga pin number function reserved reserved pqfp: 1 pbga: 0 ?151 ? the pci 6150 does not use this pin. v dd power pqfp: 28 pbga: 46 i 1, 26, 34, 40, 53, 56, 62, 69, 75, 81, 91, 97, 105, 108, 114, 120, 131, 139, 145, 157, 163, 170, 178, 184, 190, 196, 202, 208 a3, c4, d7, d8, d9, d10, e6, e7, e8, e9, e10, e11, f5, f12, g4, g5, g12, g13, h4, h5, h12, h13, j4, j5, j12, j13, k4, k5, k12, k13, l5, l12, m6, m7, m8, m9, m10, m11, n7, n8, n9, n10, p13, p15, r3, t3 +3.3v power supply. v ss ground pqfp: 28 pbga: 61 i 12, 20, 31, 37, 48, 52, 59, 66, 72, 78, 86, 94, 100, 104, 111, 117, 123, 136, 142, 148, 156, 166, 174, 181, 187, 193, 199, 205 a1, a16, b1, b2, b15, c3, c13, d4, d13, e5, e12, f6, f7, f8, f9, f10, f11, g2, g6, g7, g8, g9, g10, g11, h6, h7, h8, h9, h10, h11, j6, j7, j8, j9, j10, j11, k6, k7, k8, k9, k10, k11, l6, l7, l8, l9, l10, l11, m5, m12, n4, n13, n14, p3, p4, p14, r2, r4, r15, t1, t16 ground. total?pqfp total?pbga 57 107 section 3 pin description pinout pci 6150bb data book, version 2.11 3-20 ? 2005 plx technology, inc. all rights reserved. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 4-1 4?clocking 4 clocking this section describes the pci 6150 clocking requirements. to correctly operate, the pci 6150 requires both a primary and secondary clock. 4.1 primary and secondary clock inputs the pci 6150 implements a separate clock input for each pci interface. the primary interface is synchronized to the primary clock input, p_clkin. the secondary interface is synchronized to the secondary clock input, s_clkin. the pci 6150 operates at a maximum frequency of 66 mhz. output clocks s_clko[9:0] can be derived from p_clkin, p_clkin/2, or an external asynchronous clock source. the pci 6150 primary and secondary clock inputs can be asynchronous. there are no skew constraints between these clock inputs; however, the maximum ratio between the primary and secondary clock frequencies are 1:2.5 or 2.5:1. 4.2 secondary clock outputs the pci 6150 has ten secondary clock outputs that can be used to drive up to nine external secondary bus devices, typically, s_clko0 or s_clko4 is used to drive the pci 6150 s_clkin signal. the rules for using secondary clocks are as follows: each secondary clock output is limited to no more than one pci load at 66 mhz each clock trace length, including the feedback clock to the pci 6150 s_clkin signal, must have equal length and impedance terminate or disable unused secondary clock outputs to reduce power dissipation and noise in the system 4.3 disabling unused secondary clock outputs note: msk_in is used in the pqfp package only. if using the pbga package, use software to disable unused secondary clock buffers through the sclkcntrl; pci:68h register. when secondary clock outputs are not used, gpio[2, 0] and msk_in can be used to clock in a serial mask that selectively three-states secondary clock outputs. refer to section 14, ?gpio interface,? for details in this application. after the serial mask is shifted into the pci 6150, the mask value is readable and can be changed in the clock disable bits (sclkcntrl[13:0]; pci:68h). when the mask is modified by a configuration write operation to this register, the new clock mask disables the appropriate secondary clock outputs within a few cycles. this feature allows software to disable or enable secondary clock outputs based on the presence of option cards, and so forth. the pci 6150 delays de-asserting s_rstout#, until the serial clock mask has completely shifted in and the secondary clocks are disabled or enabled, according to the mask. the delay between p_rstin# assertion and s_rstout# de-assertion is 16 to 32 clocks. 4.3.1 secondary clock control note: msk_in is used in the pqfp package only. if using the pbga package, use software to disable unused secondary clock buffers through the sclkcntrl; pci:68h register. the pci 6150 uses the gpio[2, 0] pins and msk_in signal to input a 16-bit serial data stream. this data stream is shifted into the secondary clock control register, as soon as p_rstin# is detected de-asserted and s_rstout# is detected, and is used for selectively disabling s_clko[9:0] (sclkcntrl [13:0]; pci:68h). s_rstout# de-assertion is delayed until the pci 6150 completes shifting in the clock mask data, taking 16 clock cycles (32 cycles if operating at 66 mhz). after that, the gpio[2, 0] pins can be used as general purpose i/o pins. section 4 clocking disabling unused secondary clock outputs pci 6150bb data book, version 2.11 4-2 ? 2005 plx technology, inc. all rights reserved. an external shift register should be used to load and shift the data. (refer to figure 4-1.) the gpio[2, 0] pins are used for shift register control and serial data input, which occurs by way of a dedicated input signal, msk_in. the shift register circuitry is unnecessary for correct pci 6150 operation. the shift registers may be eliminated, and msk_in can be tied low to enable all s_clko[9:0] signals, or tied high to force all s_clko[9:0] signals high. table 4-1 delineates gpio[2, 0] pin shift register operation and table 4-2 delineates serial data formatting, based on a design where the pci 6150 secondary bus is used to drive up to four pci adapter card slots or nine devices in an embedded system. as noted in table 4-2, the first eight bits contain the philips 74f166 prsnt x [2:1]# signal (refer to figure 4-1) values for four slots, and control s_clko[3:0]. if one or both of the prsnt x [2:1]# signals are 0, a card is present in the slot and the secondary clock for that slot is not masked. if these clocks are connected to devices and not to slots, tie one or both of the bits low, to enable the clock. the next five bits are the clock device masks ( that is , each bit enables or disables the clock for one device). these bits control s_clko[8:4]?a value of 0 enables the clock, and 1 disables the clock. bit 13 is the s_clko9 clock enable bit, which is connected to the pci 6150 s_clkin. if desired, the assignment of s_clko x to slots, devices, and pci 6150 s_clkin input can be re-arranged from the assignment noted here. however, it is important that the serial data stream format match the assignment of s_clko x . the gpio[2, 0] pin serial protocol is designed to work with two philips 74f166, 8-bit bi-directional universal shift registers. the eight least significant bits, sclkcntrl[7:0], are connected to the 74f166 prsnt x [2:1]# pins for the slots. the sclkcntrl[12:8] are tied high to disable their respective secondary clocks because those clocks are not connected. sclkcntrl[13] is tied high because s_clko9 is connected to the pci 6150 s_clkin signal. figure 4-1 illustrates an example application where the pci 6150 is connected to four pci adapter card slots. the prsnt x [2:1]# pin values on the 74f166 devices are shifted into sclkcntrl[7:0]. the prsnt0[1]# value is shifted into sclkcntrl[0], prsnt0[2]# value is shifted into sclkcntrl[1], and so forth. bit 0 in the upper 74f166 is tied low, and thus enables s_clko4. in this application, s_clko4 may be used as the feedback to s_clkin. when s_rstout# is detected asserted and p_rstin# is detected de-asserted, the pci 6150 drives gpio2 low for one cycle to load the clock mask inputs into the shift register. on the next cycle, the pci 6150 drives gpio2 high to perform a shift operation. this shifts the clock mask into msk_in; the most significant bit is shifted in first, and the least significant bit is shifted in last. (refer to figure 4-2.) after the shift operation is complete, the pci 6150 places gpio[2, 0] into a high-impedance state and can de-assert s_rstout# if the secondary reset bit is clear (bcntrl[6]=0; pci:3eh). the pci 6150 then ignores msk_in, and gpio signal control reverts to the pci 6150 gpio control registers. the clock disable bits can be subsequently modified through a configuration write command to the secondary clock control register (sclkcntrl; pci:68h) in device-specific configuration space. table 4-1. gpio shift register operation pin operation gpio0 shift register clock output at 66 mhz maximum frequency. gpio1 not used. gpio2 shift register control. values: 0 = load 1 = shift gpio3 not used. section 4 disabling unused secondary clock outputs clocking pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 4-3 4?clocking table 4-2. gpio serial data format sclkcntrl[15:0] description s_clko[9:0] 1:0 slot 0 74f166 prsnt0[2:1]# or device 0 0 3:2 slot 1 74f166 prsnt1[2:1]# or device 1 1 5:4 slot 2 74f166 prsnt2[2:1]# or device 2 2 7:6 slot 3 74f166 prsnt3[2:1]# or device 3 3 8 device 4 4 9 device 5 5 10 device 6 6 11 device 7 7 12 device 8 8 13 device 9 9 15:14 reserved ? section 4 clocking disabling unused secondary clock outputs pci 6150bb data book, version 2.11 4-4 ? 2005 plx technology, inc. all rights reserved. figure 4-1. gpio clock mask implem entation on system board example notes: * pulling the upper 74f166 bit 0 low enables s_clko4. in the philips 74f166 prsntx# signals, x indicates the slot number, and the number in brackets indicates the appropriate prsnt# signal (for example, prsnt0[1]# is signal prsnt1# of slot 0). figure 4-2. clock mask and load shift timing pci 6150 q7 74f166 q7 74f166 msk_in gpio0 gpio2 v ss v cc v ss v cc ce# cp mr# pe 7 6 5 4 3 2 1 0 ce# cp mr# pe 7 6 5 4 3 2 1 *0 prsnt3[2]# prsnt3[1]# prsnt2[2]# prsnt2[1]# prsnt1[2]# prsnt1[1]# prsnt0[2]# prsnt0[1]# d s bit 15 bit 14 bit 13 bit 12 bit 11 gpio0 gpio2 msk_in section 4 frequency division options clocking pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 4-5 4?clocking 4.4 frequency division options the pci 6150 has built-in frequency division options to automatically adjust the s_clko[9:0] clocks for pci 33 or 66 mhz operation. table 4-3 lists the clock division ratios used, depending on the p_m66en and s_m66en signal states. note: s_m66en cannot be floating. 4.5 using an external clock source the pci 6150 uses two signals?oscsel# and oscin?when connecting an external clock source to the pci 6150. during normal operation, the pci 6150 generates s_clko[9:0], based on the pci clock source (p_clkin). if oscsel# is asserted (low), then the pci 6150 derives s_clko[9:0] from the oscin signal instead. clock division is performed on the oscin and p_clkin clocks, depending on the p_m66en and s_m66en signal states. 4.6 running secondary port faster than primary port the pci 6150 allows the secondary port to use a higher clock frequency than that of the primary port. in this case, a secondary clock source, using an external oscillator or clock generator, must be provided. if the external oscillator is connected to oscin and oscsel# is asserted (low), then the output generated by s_clko[9:0] is divided, as per table 4-3. division control can be disabled by pulling s_m66en high and not connecting this pin to a pci slot (which may be on the secondary bus). if the s_clko[9:0] outputs are not required, then the external clock can be fed directly into the s_clkin signal. table 4-3. pci clock frequency division ratios p_m66en value s_m66en value pci clock frequency division ratio 111/1 101/2 011/1 001/1 pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 5-1 5?reset and initialization 5 reset and initialization this section describes 66 mhz operation, primary, secondary, and power management reset, and register initialization. note: jtag reset is discussed in section 21.1.4, ?jtag reset input trst#.? 5.1 66 mhz operation note: cfg66 is used in the pqfp package only. in the pbga package, the 66 mhz-capable bits are hardwired to 1 (pcisr[5]=1; pci:06h and pcissr[5]=1; pci:1eh) to indicate 66 mhz capability. the pci 6150 supports up to 66 mhz operation. the cfg66 and p_m66en pin inputs should be high for 66 mhz operation. the cfg66 signal must be tied high on the board to enable 66 mhz operation and to set the status register 66 mhz capable bits in configuration space (pcisr[5]=1; pci:06h and pcissr[5]=1; pci:1eh). the p_m66en and s_m66en signals indicate whether the primary and secondary interfaces, respectively, are operating at 66 mhz. this information is needed to control the secondary bus frequency. per pci r2.3 , for clock frequencies between 33 and 66 mhz, the clock frequency may not change except while p_rstin# is asserted, or when spread spectrum clocking (ssc) is used to reduce emi emissions. the following primary and secondary bus frequency combinations are supported when using the primary p_clkin signal to generate secondary clock outputs: 66 mhz primary bus, 66 mhz secondary bus 66 mhz primary bus, 33 mhz secondary bus 33 mhz primary bus, 33 mhz secondary bus if p_m66en is low ( for example , the primary bus runs at 33 mhz), the pci 6150 drives s_m66en low to indicate that the secondary bus is operating at 33 mhz. if the secondary bus is set to run faster than the primary bus, s_m66en need not be connected to secondary pci devices. the pci 6150 can also generate s_clko[9:0] from oscin, if enabled. when the pci 6150 is running with external clock input that is not generated from s_clko[9:0], the p_m66en- and s_m66en- controlled clock division does not apply. when oscin or other external clock inputs are used for the secondary port, the pci 6150 can run with a maximum ratio of 1:2.5 or 2.5:1 between the primary and secondary bus clocks. for further details, refer to section 4.4, ?frequency division options,? and section 4.6, ?running secondary port faster than primary port.? 5.2 reset this subsection describes the primary and secondary interface and chip reset mechanisms. the pci 6150 has two reset mechanisms and two reset pins? p_rstin# and s_rstout#. (refer to table 5-1.) in addition, the pci 6150 can respond to power management-initiated internal resets. after the reset signals are de-asserted, the pci 6150 requires 256 clocks to initialize bridge functions. during this initialization, type 0 accesses can be accepted. however, no memory nor i/o transactions are allowed through the bridge during this time. table 5-1. reset input sources reset inputs function p_rstin# resets primary and secondary ports causes s_rstout# to be active causes serial eeprom load s_rstout# not used as input chip reset (dcntrl[0]=1; pci:41h) resets internal state machines secondary reset (bcntrl[6]=1; pci:3eh) resets only secondary port causes s_rstout# to be active section 5 reset and initialization reset pci 6150bb data book, version 2.11 5-2 ? 2005 plx technology, inc. all rights reserved. 5.2.1 primary reset input to properly reset, the pci 6150 requires at least two clocks before the p_rstin# rising edge. when p_rstin# is asserted, the following events occur: 1. pci 6150 immediately places all primary pci interface signals into a high-impedance state. 2. all registers are reset. 3. p_rstin# assertion automatically causes a secondary port reset. forty-three clocks after p_rstin# goes high, s_rstout# goes high. 4. clock disable bits begin shifting in at the rising edge of p_rstin#. the asserting and de-asserting edges of p_rstin# can be asynchronous to p_clkin and s_clkin. the p_rstin# asserting and de-asserting edges can be asynchronous to p_clkin and s_clkin. the pci 6150 requires 256 primary port pci clocks after p_rstin# rising edge to reset its internal logic. when p_rstin# is asserted, all primary pci interface signals, including the primary request output, are immediately placed into a high-impedance state. all posted write and delayed transaction data buffers are reset. therefore, transactions residing in the buffers are discarded upon p_rstin# assertion. 5.2.2 secondary reset output the pci 6150 is responsible for driving the secondary bus reset signal, s_rstout#. the pci 6150 asserts s_rstout# when any of the following conditions are met: p_rstin# asserted s_rstout# remains asserted if p_rstin# is asserted and does not de-assert until p_rstin# is de-asserted. bridge control register secondary reset bit is set (bcntrl[6]=1; pci:3eh) s_rstout# remains asserted until bcntrl[6]=0. when s_rstout# is asserted, all secondary pci interface control signals, including s_gnt[8:0]#, are immediately placed into a high-impedance state. s_ad[31:0], s_cbe[3:0]#, and s_par are driven low for the duration of s_rstout# assertion. all posted write and delayed transaction data buffers are reset; therefore, any transactions residing in buffers at the time of secondary reset are discarded. when s_rstout# is asserted by means of the secondary reset bit, the pci 6150 remains accessible during secondary interface reset and continues to respond to configuration space accesses from the primary interface. 5.2.3 jtag reset refer to section 21.1.4, ?jtag reset input trst#.? 5.2.4 software resets the diagnostic control register chip reset bit can be used to reset the pci 6150 (dcntrl[0]=1; pci:41h). this action causes s_rstout# assertion; however, the signals are not placed into a high-impedance state. when the chip reset bit is set, all registers and chip states are reset. when chip reset completes, within four pci clock cycles after completion of the configuration write operation that sets the chip reset bit, the chip reset bit automatically clears and the pci 6150 is ready for configuration. during chip reset, the pci 6150 is inaccessible. 5.2.5 power manageme nt internal reset . when there is a d 3hot -to-d 0 transition with the power management control/status register power state bits programmed to d 0 (pmcsr[1:0]=00b; pci:e0h), an internal reset equivalent to p_rstin# is generated and all relevant registers are reset. however, s_rstout# is not asserted. section 5 register initialization reset and initialization pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 5-3 5?reset and initialization 5.3 register initialization the pci 6150 configuration registers may be initialized in one of three ways: default values serial eeprom contents host initialization 5.3.1 default initialization after p_rstin# de-assertion, the pci 6150 automatically checks for a valid a serial eeprom. if the serial eeprom is not valid nor present, the pci 6150 automatically loads default values into the configuration registers. (refer to the ?value after reset? column of the register tables in section 6, ?registers.?) 5.3.2 serial eeprom initialization after p_rstin# de-assertion, if the pci 6150 finds a valid serial eeprom, register values are loaded from the serial eeprom and overwrite the default values. (refer to section 7.3, ?serial eeprom autoload mode at reset.?) 5.3.3 host initialization when device initialization is complete, the host system may access the appropriate registers to configure them according to system requirements. typically, registers are accessed by performing type 0 configuration accesses from the appropriate bus. for details regarding register access, refer to section 6, ?registers.? note: not all registers may be written to nor available from both sides of the bridge. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-1 6?registers 6 registers this section describes the pci 6150 pci registers. the pci 6150 includes the standard type 01h configuration space header, as defined in p-to-p bridge r1.1 . note: registers listed with a pci of fset or address are accessed by standard pci type 0 configuration accesses. 6.1 pci configuration register address mapping table 6-1. pci configuration register address mapping pci configuration register address to ensure software compatibility with other versions of the pci 6150 family and to ensure compatibility with future enhancements, write 0 to all unused bits. pci writable serial eeprom writable 31 24 23 16 15 8 70 00h device id* vendor id* yes yes 04h primary status primary command yes no 08h class code* revision id yes yes 0ch built-in self-test* header type* primary latency timer cache line size yes yes 10h ? 17h reserved no no 18h secondary latency timer subordinate bus number secondary bus number primary bus number yes no 1ch secondary status i/o limit i/o base yes no 20h memory limit memory base yes no 24h prefetchable memory limit prefetchable memory base yes no 28h prefetchable memory base upper 32 bits yes no 2ch prefetchable memory limit upper 32 bits yes no 30h i/o limit upper 16 bits i/o base upper 16 bits yes no 34h reserved new capability pointer (dch if power management support; otherwise, e4h) no no 38h reserved no no 3ch bridge control interrupt pin reserved yes no 40h arbiter control diagnostic control chip control yes no 44h miscellaneous options timeout control primary flow- through control yes yes 48h secondary incremental prefetch count primary incremental prefetch count secondary prefetch line count primary prefetch line count yes yes 4ch reserved secondary flow- through control secondary maximum prefetch count primary maximum prefetch count yes yes section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-2 ? 2005 plx technology, inc. all rights reserved. notes: * writable only when the read-only registers write enable bit is set (rrc[7]=1; pci:9ch). .refer to the individual register descriptions to determine which bits are writable. 50h reserved test internal arbiter control yes no 54h serial eeprom data serial eeprom address serial eeprom control yes no 58h ? 63h reserved no no 64h gpio[3:0] input data gpio[3:0] output enable gpio[3:0] output data p_serr# event disable yes no 68h reserved p_serr# status secondary clock control yes no 6ch ? 98h reserved no no 9ch reserved read-only register control yes no a0h ? d8h reserved yes no dch power management capabilities* power management next capability pointer (e4h) power management capability id (01h) yes yes e0h power management data* pmcsr bridge supports extensions power management control/status* yes yes e4h reserved hot swap control/ status (0h) hot swap next capability pointer (e8h) hot swap control (capability id) (06h) yes no e8h vpd address (0h) vpd next capability pointer (00h) vpd capability id (03h) yes no ech vpd data (0h) yes no table 6-1. pci configuration register address mapping (continued) pci configuration register address to ensure software compatibility with other versions of the pci 6150 family and to ensure compatibility with future enhancements, write 0 to all unused bits. pci writable serial eeprom writable 31 24 23 16 15 8 70 section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-3 6?registers 6.1.1 pci type 1 header register 6-1. (pciidr; pci:00h) pci configuration id bit description read write value after reset 15:0 vendor id. identifies pci 6150 manufacturer. defaults to the pci-sig-issued plx vendor id (3388h), if a blank or no serial eeprom is present. yes only if rrc[7]=1; serial eeprom 3388h 31:16 device id. identifies the particular device. defaults to plx pci 6150 part number (0022h), if a blank or no serial eeprom is present. yes only if rrc[7]=1; serial eeprom 0022h section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-4 ? 2005 plx technology, inc. all rights reserved. register 6-2. (pcicr; pci:04h) primary pci command bit description read write value after reset 0 i/o space enable. controls bridge response to i/o accesses on primary interface. values: 0 = ignores i/o transactions 1 = enables response to i/o transactions yes yes 0 1 memory space enable. controls bridge response to memory accesses on primary interface. values: 0 = ignores memory transactions 1 = enables response to memory transactions yes yes 0 2 bus master enable. controls bridge ability to operate as a master on primary interface. values: 0 = does not initiate transactions on primary interface and disables response to memory or i/o transactions on secondary interface 1 = enables bridge to operate as a master on primary interface yes yes 0 3 special cycle enable. not supported. yes no 0 4 memory write and invalidate enable. not supported. yes no 0 5 vga palette snoop enable. controls bridge response to vga-compatible palette accesses. values: 0 = ignores vga palette accesses on primary interface 1 = enables response to vga palette writes on primary interface (i/o address ad[9:0]=3c6h, 3c8h, and 3c9h) note: if bcntrl[3]=1; pci:3eh (vga enable bit), then vga palette accesses are forwarded, regardless of the pcicr[5] value. yes yes 0 6 parity error response enable. controls bridge response to parity errors. values: 0 = ignores parity errors 1 = performs normal parity checking yes yes 0 7 wait cycle control. if set to 1, the pci 6150 performs address/data stepping. yes yes 1 8 p_serr# enable. controls the primary system error (p_serr#) pin enable. values: 0 = disables p_serr# driver 1 = enables p_serr# driver yes yes 0 9 fast back-to-back enable. controls bridge ability to generate fast back-to-back trans actions to various devices on secondary interface. values: 0 = no fast back-to-back transactions 1 = enables fast back-to-back transactions yes yes 0 15:10 reserved. yes no 0h section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-5 6?registers register 6-3. (pcisr; pci:06h) primar y pci status bit description read write value after reset 3:0 reserved. yes no 0h 4 new capability functions support. writing 1 supports new capabilities functions. the new capability function id is located at the pci configuration space offset, determined by the new capabilities linked list pointer value at cap_ptr; pci:34h. yes no 1 5 66 mhz-capable. if set to 1, this device supports a 66 mhz pci clock environment. reflects cfg66 pin state. note: hardwired to 1 in the pbga package. yes no 1 6 udf. no user-definable features. yes no 0 7 fast back-to-back capable. fast back-to-back write capable on primary port. set to 1. yes no 0 8 data parity error detected. set when the following conditions are met: p_perr# is asserted, and command register parity error response enable bit is set (pcicr[6]=1; pci:04h) writing 1 clears bit to 0. yes yes/clr 0 10:9 devsel# timing . reads as 01b to indicate pci 6150 responds no slower than with medium timing. yes no 01b 11 signaled target abort. set by a target device when a target abort cycle occurs. writing 1 clears bit to 0. yes yes/clr 0 12 received target abort. set to 1 by the pci 6150 when transactions are terminated with target abort. writing 1 clears bit to 0. yes yes/clr 0 13 received master abort. set to 1 by the pci 6150 when transactions are terminated with master abort. writing 1 clears bit to 0. yes yes/clr 0 14 signaled system error. set when p_serr# is asserted. writing 1 clears bit to 0. yes yes/clr 0 15 parity error detected. set when a parity error is detected, regardless of the parity error response enable bit state (pcicr[6]=x; pci:04h). writing 1 clears bit to 0. yes yes/clr 0 section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-6 ? 2005 plx technology, inc. all rights reserved. register 6-4. (pcirev; pci:08h) pci revision id bit description read write value after reset 7:0 revision id. pci 6150 silicon revision. yes no 04h register 6-5. (pciccr; pci:09h ? 0bh) pci class code bit description read write value after reset 7:0 register level programming interface. none defined. yes only if rrc[7]=1; serial eeprom; serial eeprom 0h 15:8 subclass code. pci-to-pci bridge or other bridge device. yes only if rrc[7]=1; serial eeprom; serial eeprom 04h 23:16 base class code. bridge device. yes only if rrc[7]=1; serial eeprom; serial eeprom 06h section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-7 6?registers note: pcihtr is hardcoded to 01h. register 6-6. (pciclsr; pc i:0ch) pci cache line size bit description read write value after reset 7:0 system cache line size. specified in units of 32-bit words (dwords). only cache line sizes of a power of two are valid. maximum value is 20h. for values greater than 20h, pci 6150 operates as if pcicls r is programmed with value of 08h. used when terminating memory write and invalidate transactions and prefetching. memory read prefetching is controlled by the prefetch count registers. note: only one bit can be set in this register. yes yes 0h register 6-7. (pciltr; pci:0dh) primary pci bus latency timer bit description read write value after reset 7:0 primary pci bus latency timer. specifies amount of time (in units of pci bus clocks) the pci 6150, as a bus master, can burst data on the primary pci bus. time counting begins when the master asserts p_frame#. yes yes 0h register 6-8. (pcihtr; pci:0eh) pci header type bit description read write value after reset 6:0 configuration layout type. specifies register layout at offsets 10h to 3fh in configuration space. header type 0 is defined for pci devices ot her than pci-to-pci bridges (header type 1) and cardbus bridges (header type 2). yes only if rrc[7]=1; serial eeprom 1h 7 multi-function device. value of 1 indicates multiple (up to eight) functions (logical devices), each containing its own, individually addressable configuration space, 64 dwords in size. yes only if rrc[7]=1; serial eeprom 0 register 6-9. (pcibistr; pci:0fh) pci built-in self-test bit description read write value after reset 7:0 built-in self-test (bist). can only be programmed by serial eeprom. yes only if rrc[7]=1; serial eeprom 0h section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-8 ? 2005 plx technology, inc. all rights reserved. register 6-10. (pcipbno; pci:18h) pci primary bus number bit description read write value after reset 7:0 primary bus number. programmed with the pci bus number to which the primary bridge interface is connected. value is set with configuration software. yes yes 0h register 6-11. (pcisbno; pci:19h) pci secondary bus number bit description read write value after reset 7:0 secondary bus number. programmed with the pci bus number to which the secondary bridge interface is connected. value is set with configuration software. yes yes 0h register 6-12. (pcisubno; pci: 1ah) pci subordinate bus number bit description read write value after reset 7:0 subordinate bus number. programmed with the pci bus number with the highest number subordinate to the bridge. value is set with configuration software. yes yes 0h register 6-13. (pcisltr; pci:1bh) secondary pci bus latency timer bit description read write value after reset 7:0 secondary pci bus latency timer. specifies the amount of time (in units of pci bus clocks) the pci 6150, as a bus master, can burst data on the secondary pci bus. latency timer checks for master accesses on the secondary bus that remain unclaimed by targets. yes yes 0h section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-9 6?registers register 6-14. (pciiobar; pci:1ch) i/o base bit description read write value after reset 7:0 i/o base. specifies the i/o base address range bits [15:12] for forwarding the cycle through the bridge (base address bits [11:0] are assumed to be 0h). used in conjunction with the i/o limit, i/o base upper 16 bits, and i/o limit upper 16 bits registers (pciiolmt; pci:1dh, pciiobaru16; pci:30h, and pciiolmtu16; pci:32h, respectively) to specify a r ange of 32-bit addresses supported for pci bus i/o transactions. the lower four read-only bi ts [3:0] are hardcoded to 0001b to indicate 32-bit i/o addressing support. yes yes [7:4] 1h register 6-15. (pciiolmt; pci:1dh) i/o limit bit description read write value after reset 7:0 i/o limit. specifies the upper i/o limit address range bits [15:12] for forwarding the cycle through the bridge (limit address bits [11:0] are assumed to be fffh). used in conjunction with the i/o base, i/o base upper 16 bits, and i/o limit upper 16 bits registers (pciiobar; pci:1ch, pciiobaru16; pci:30h, and pciiolmtu16; pci:32h, respectively) to specify a range of 32-bit addresses supported for pci bus i/o transactions. the lower four read-only bi ts [3:0] are hardcoded to 0001b to indicate 32-bit i/o addressing support. yes yes [7:4] 1h section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-10 ? 2005 plx technology, inc. all rights reserved. register 6-16. (pcissr; pci:1eh) secondary pci status bit description read write value after reset 4:0 reserved. yes no 0h 5 66 mhz-capable. if set to 1, the pci 6150 supports a 66 mhz pci clock environment. reflects cfg66 pin state. note: hardwired to 1 in the pbga package. yes no 1 6 udf. no user-definable features. yes no 0 7 fast back-to-back capable. fast back-to-back write capable on secondary port. set to 1. yes no 0 8 data parity error detected. set when the following conditions are met: s_perr# is asserted, and command register parity error response enable bit is set (pcicr[6]=1; pci:04h) writing 1 clears bit to 0. yes yes/clr 0 10:9 devsel# timing . reads as 01b to indicate pci 6150 responds no slower than with medium timing. yes no 01b 11 signaled target abort. set by a target device when a target abort cycle occurs. writing 1 clears bit to 0. yes yes/clr 0 12 received target abort. set to 1 by pci 6150 when transactions are terminated with target abort. writing 1 clears bit to 0. yes yes/clr 0 13 received master abort. set to 1 by pci 6150 when transactions are terminated with master abort. writing 1 clears bit to 0. yes yes/clr 0 14 signaled system error. set when s_serr# is asserted. writing 1 clears bit to 0. yes yes/clr 0 15 parity error detected. set when a parity error is detected, regardless of the parity error response enable bit state (pcicr[6]=x]; pci:04h). writing 1 clears bit to 0. yes yes/clr 0 section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-11 6?registers register 6-17. (pcimbar; pci:20h) memory base bit description read write value after reset 15:0 memory base. specifies the memory-mapped i/o base address range bits [31:20] for forwarding the cycle through the bridge. the upper 12 bits corresponding to [31:20] are writable. the lower 20 address bits [19:0] are assumed to be 0h. used in conjunction with the memory limit register (pcimlmt; pci:22h) to specify a range of 32-bit addresses supported for pci bus memory-mapped i/o transactions. the lower four read-only bits [3:0] are hardcoded to 0h. yes yes [15:4] 0h register 6-18. (pcimlmt; pci:22h) memory limit bit description read write value after reset 15:0 memory limit. specifies the upper memory-mapped i/o limit address range bits [31:20] for forwarding the cycle through the bridge. the upper 12 bits corresponding to [31:20] are writable. the lower 20 address bits [19:0] are assumed to be f_ffffh. used in conjunction with the memory base register (pcimbar; pci:20h) to specify a range of 32-bit addresses supported for pci bus memory- mapped i/o transactions. the lower four read-only bits [3:0] are hardcoded to 0h. yes yes [15:4] 0h section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-12 ? 2005 plx technology, inc. all rights reserved. register 6-19. (pcipmbar; pci: 24h) prefetchable memory base bit description read write value after reset 15:0 prefetchable memory base. specifies the prefetchable memory-mapped base address range bits [31:20] for forwarding the cycle through the bridge. the upper 12 bits corresponding to [31:20] are writable. the lower 20 address bits [19:0] are assumed to be 0h. used in conjunction with the prefetchable memory limit, prefetchable memory base upper 32 bits, and prefetchable memory limit upper 32 bits registers (pcipmlmt; pci:26h, pcipmbaru32; pci:28h, and pcipmlmtu32; pci:2ch, respectively) to specify a r ange of 64-bit addresses supported for prefetchable memory transactions on the pci bus. the lower four read-only bits [3:0] are hardcoded to 01h, indicating 64-bit address support. yes yes [15:4] 1h register 6-20. (pcipmlmt; pci: 26h) prefetchable memory limit bit description read write value after reset 15:0 prefetchable memory limit. specifies the upper prefetchable memory-mapped limit address range bits [31:20] for forwarding the cycle through the bridge. the lower 20 address bits [19:0] are assumed to be f_ffffh. used in conjunction with the prefetchable memory base, prefetchable memory base upper 32 bits, and prefetchable memory limit upper 32 bits registers (pcipmbar; pci:24h, pcipmbaru32; pci:28h, and pcipmlmtu32; pci:2ch, respectively) to specify a r ange of 64-bit addresses supported for prefetchable memory transactions on the pci bus. the lower four read-only bits [3:0] are hardcoded to 01h, indicating 64-bit address support. yes yes [15:4] 1h section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-13 6?registers register 6-21. (pcipmbaru32; pci:28h) prefetchable memory base upper 32 bits bit description read write value after reset 31:0 prefetchable memory base upper 32 bits. specifies the upper prefetchable memory-mapped base address range bits [63:32] for forwarding the cycle through the bridge. the lower 20 address bits [19:0] are assumed to be 0h. used in conjunction with the prefetchable memory base, prefetchable memory limit, and prefetchable memory limit upper 32 bits registers (pcipmbar; pci:24h, pcipmlmt; pci:26h, and pcipmlmtu32; pci:2ch, respectively) to specify a range of 64-bit addresses supported for prefetchable memory transactions on the pci bus. yes yes 0h register 6-22. (pcipmlmtu32; pci:2ch) prefetchable memory limit upper 32 bits bit description read write value after reset 31:0 prefetchable memory limit upper 32 bits. specifies the upper prefetchable memory-mapped limit address range bits [63:32] for forwarding the cycle through the bridge. the lower 20 address bits [19:0] are assumed to be f_ffffh. used in conjunction with the prefetchable memory base, prefetchable memory limit, and prefetchable memory base upper 32 bits registers (pcipmbar; pci:24h, pcipmlmt; pci:26h, and pcipmbaru32; pci:28h, respectively) to specify a range of 64-bit addresses supported for prefetchable memory transactions on the pci bus. yes yes 0h section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-14 ? 2005 plx technology, inc. all rights reserved. register 6-23. (pciiobaru16; pci:30h) i/o base upper 16 bits bit description read write value after reset 15:0 i/o base upper 16 bits. specifies the upper i/o base address range bits [31:16] for forwarding the cycle through the bridge. base address bits [11:0] are assumed to be 0h. used in conjunction with the i/o base, i/o limit, and i/o limit upper 16 bits registers (pciiobar; pci:1ch, pciiolmt; pci:1dh, and pciiolmtu16; pci:32h, respectively) to specify a range of 32-bit addresses supported for pci bus i/o transactions. yes yes 0h register 6-24. (pciiolmtu16; pci:32h) i/o limit upper 16 bits bit description read write value after reset 15:0 i/o limit upper 16 bits. specifies the upper i/o limit address range bits [31:16] for forwarding the cycle through the bridge. limit address bits [11:0] are assumed to be fffh. used in conjunction with the i/o base, i/o limit, and i/o base upper 16 bits registers (pciiobar; pci:1ch, pciiolmt; pci:1dh, and pciiobaru16; pci:30h, respectively) to specify a range of 32-bit addresses supported for pci bus i/o transactions. yes yes 0h register 6-25. (cap_ptr; pci:34h) new capability pointer bit description read write value after reset 7:0 new capability pointer. provides an offset into pci configuration space for the next capability location in the new capabilities linked list. if the selected device id supports power management, the value defaults to dch. otherwise, the value defaults to e4h (for hot swap). . yes no dch (pm) or e4h (hot swap) 31:8 reserved. yes no 0h section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-15 6?registers register 6-26. (pciipr; pci:3dh) pci interrupt pin bit description read write value after reset 7:0 interrupt pin. reads as 0h to indicate that pci 6150 does not use interrupt pins. yes no 0h register 6-27. (bcntrl; pci:3eh) bridge control bit description read write value after reset 0 parity error response enable. controls bridge response to parity errors on secondary interface. values: 0 = ignores address and data parity errors on secondary interface 1 = enables parity error reporting and detection on secondary interface yes yes 0 1 s_serr# enable. controls forwarding of s_serr# to primary interface. values: 0 = disables s_serr# forwarding to primary 1 = enables s_serr# forwarding to primary yes yes 0 2 isa enable. controls bridge response to isa i/o addresses, which is limited to the first 64 kb. values: 0 = forwards i/o addresses in the range defined by the i/o base and limit registers (pciiobar; pci:1ch and pciiolmt; pci:1dh, respectively). 1 = blocks forwarding of isa i/o addresses in the range defined by the i/o base and limit registers in the first 64 kb of i/o space that address the last 768 bytes in each 1-kb block. secondary i/o transactions are forwarded upstream, if the address falls within the last 768 bytes in each 1-kb block. command configuration register master enable bit must also be set (pcicr[2]=1; pci:04h) to enable isa. note: there is an isa enable control bit write protect mechanism controlled by serial eeprom. when set in serial eeprom, and serial eeprom initialization is enabled, pci 6150 changes this bit to read-only and the isa-enable feature is not available. yes yes 0 3 vga enable. controls bridge response to vga-compatible addresses. values: 0 = does not forward vga-compatible memory nor i/o addresses from primary to secondary 1 = forwards vga-compatible memory and i/o addresses from primary to secondary, regardless of other settings note: if set to 1, then i/o addresses in the range of 3b0h to 3bbh and 3c0h to 3dfh are forwarded, regardless of the pcicr[5]; pci:04h or bcntrl[2] values. yes yes 0 section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-16 ? 2005 plx technology, inc. all rights reserved. 4 reserved yes no 0 5 master abort mode. controls bridge behavior in response to master aborts on secondary interface. values: 0 = does not report master aborts (return ffff_ffffh on reads or discard data on writes). 1 = reports master aborts by signaling target abort. if the master abort is the result of a primary-to-secondary posted write cycle, p_serr# is asserted (pcicr[8]=1; pci:04h). note: during lock cycles, pci 6150 ignores this bit, and completes the cycle as a target abort. yes yes 0 6 secondary reset. forces s_rstout# assertion on secondary interface. values: 0 = does not force s_rstout# assertion 1 = forces s_rstout# assertion yes yes 0 7 fast back-to-back enable. controls bridge ability to generate fast back-to-back transactions to various devices on secondary interface. values: 0 = no fast back-to-back transactions 1 = enables fast back-to-back transactions yes yes 0 8 primary master timeout (discard timer). sets the maximum number of pci clocks for an initiator on the primary bus to repeat the delayed transaction request. values: 0 = timeout after 2 15 pci clocks 1 = timeout after 2 10 pci clocks yes yes 0 9 secondary master timeout (discard timer). sets the maximum number of pci clocks for an initiator on the secondary bus to repeat the delayed transaction request. values: 0 = timeout after 2 15 pci clocks 1 = timeout after 2 10 pci clocks yes yes 0 10 master timeout status. set to 1 when primary or secondary master timeout occurs. writing 1 clears bit to 0. yes yes/clr 0 11 master timeout p_serr# enable. enable p_serr# assertion during master timeout. values: 0 = p_serr# not asserted on master timeout 1 = p_serr# asserted on primary or secondary master timeout yes yes 0 15:12 reserved. yes no 0h register 6-27. (bcntrl; pci:3e h) bridge control (continued) bit description read write value after reset section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-17 6?registers 6.1.2 device-specific 6.1.2.1 chip, diagnostic , and arbiter control register 6-28. (ccntrl; pci:40h) chip control bit description read write value after reset 0 reserved. yes no 0 1 memory write disconnect control. controls when pci 6150, as a target, disc onnects memory transactions. values: 0 = disconnects on queue full or on a 4-kb boundary 1 = disconnects on a cache line boundary, when the queue fills, or on a 4-kb boundary yes yes 0 2 i/o 1-kb decode. values: 0 = i/o decodes to 1-kb resolution 1 = i/o decodes to 4-kb resolution yes yes 0 3 reserved. yes no 0 4 secondary bus prefetch disable. controls pci 6150 ability to prefetch during upstream memory read transactions. values: 0 = prefetches and does not fo rward byte enables during memory read transactions. 1 = requests only 1 dword from the target during memory read transactions and forwards byte enables. pci 6150 returns a target disconnect to the requesting master on the first data transfer. memory read line and memory read multiple transactions remain prefetchable. yes yes 0 7:5 reserved. yes no 000b section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-18 ? 2005 plx technology, inc. all rights reserved. register 6-29. (dcntrl; pc i:41h) diagnostic control bit description read write value after reset 0 chip reset. chip and secondary bus reset. setting bit activates full chip reset, asserts s_rstout#, and forces the bridge control register secondary reset bit to be set (bcntrl[6]=1; pci:3eh). after resetting the pci 6150 registers, bit is cleared; however, bcntrl[6] remains set to 1. writing 0 has no effect. yes yes 0 2:1 reserved and must be set to 00b. yes yes 00b 3 secondary reset output mask. not supported .yesno0 7:4 reserved. yes no 0h register 6-30. (acntrl; pci:42h) arbiter control bit description read write value after reset 8:0 arbiter control. each bit controls whether a secondary bus master is assigned to the high- or low-priority group. bits [8:0] correspond to request inputs s_req[8:0]#, respectively. value of 1h assigns the bus master to the high-priority group. note: s_req0# is an i/o pin. yes yes 0 11:9 reserved. yes no 0 12 primary port ordering rule. reserved and must be set to 0. yes yes 0 13 secondary port ordering rule. reserved and must be set to 0. yes yes 0 15:14 reserved and must be set to 0. yes no 0h section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-19 6?registers 6.1.2.2 primary flow-through control register 6-31. (pftcr; pci:44h) primary flow-through control bit description read write value after reset 2:0 primary posted write completion wait count. maximum number of clocks the pci 6150 waits for posted write data from the initiator if delivering write data in flow-through mode and the internal post write queues are almost empty. if the count is exceeded without additional data from the initiator, the cycle to the target is terminated and later completed. values: 000b = terminates the cycle if there is only one data entry remaining in the internal write queue 001b = de-asserts s_irdy# and waits one clock for source data on the primary bus, before terminating cycle ? 111b = de-asserts s_irdy# and waits seven clocks for source data on the primar y bus, before terminating cycle yes yes; serial eeprom 111b 3 reserved. returns 00b when read. yes no 0 6:4 primary delayed read completion wait count. maximum number of clocks the pci 6150 waits for delayed read data from the target, if returning read data in flow-through mode and the internal delayed read queue is almost full. if the count is exceeded without additional space in the queue, the cycle to target is terminated, and completed when the initiator retries the remainder of the cycle. values: 000b = terminates the cycle if there is only one data entry remaining in the read queue 001b = de-asserts s_trdy# and waits one clock for source data on the primary bus, before terminating cycle ? 111b = de-asserts s_trdy# and waits seven clocks for source data on the primary bus, before terminating cycle yes yes; serial eeprom 111b 7 reserved. returns 00b when read. yes no 0 section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-20 ? 2005 plx technology, inc. all rights reserved. 6.1.2.3 timeout control register 6-32. (tocntrl; pci:45h) timeout control bit description read write value after reset 2:0 maximum retry counter control. controls the maximum number of times the pci 6150 retries a cycle before signaling a timeout. timeout applies to read/write retries and can be enabled to trigger serr# on the primary or secondary port, depending on the serr# events enabled. maximum number of retries to timeout: 000b = 2 24 001b = 2 18 010b = 2 12 011b = 2 6 111b = 2 0 yes yes; serial eeprom 000b 3 reserved. yes no 0 5:4 primary master timeout divider. provides additional options for the primary master timeout. in addition to its original setting in the bridge control register (bcntrl[8]; pci:3eh), the timeout counter can optionally be divided by up to 256: 00b = counter?primary master timeout / 1 01b = timeout counter?primary master timeout / 8 10b = timeout counter?primary master timeout / 16 11b = timeout counter?primary master timeout / 256 bcntrl[8] can set the primary master timeout to 32k (default) or 1k clock cycles. yes yes; serial eeprom 00b 7:6 secondary master timeout divider. provides additional options for the secondary master timeout. in addition to its original setting in the bridge control register (bcntrl[9]; pci:3eh), the timeout counter can optionally be divided by up to 256: 00b = counter?secondary master timeout / 1 01b = timeout counter?secondary master timeout / 8 10b = timeout counter?secondary master timeout / 16 11b = timeout counter?secondary master timeout / 256 bcntrl[9] can set the secondary master timeout to 32k (default) or 1k clock cycles. yes yes; serial eeprom 00b section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-21 6?registers 6.1.2.4 miscellaneous options register 6-33. (mscopt; pci:46h) miscellaneous options bit description read write value after reset 0 write completion wait for perr#. if set to 1, pci 6150 waits for target perr# status before completing a delayed write transaction to the initiator. yes yes; serial eeprom 0 1 read completion wait for par. if set to 1, pci 6150 waits for target par status before completing a delayed read transaction to the initiator. yes yes; serial eeprom 0 2 delayed read transaction (drt) out-of-order enable. if set to 1, pci 6150 may return delayed read transactions in a different order than reques ted. otherwise, delayed read transactions are returned in the same order as requested. yes yes; serial eeprom 0 3 generate parity enable. if set to 1, pci 6150 (as a master) generates par to cycles going across the bridge. otherwise, pci 6150 passes along the par of the cycle as stored in the internal buffers. yes yes 0 6:4 address step control. during type 0 configuration cycles, pci 6150 drives the address for the number of clocks specified by these bits, before asserting frame#. defaults to 001b in conventional pci mode. values: 000b = concurrently asserts fr ame# and drives the address on the bus 001b = asserts frame# one clock after driving the address on the bus ? 111b = asserts frame# seven clocks after driving the address on the bus yes yes; serial eeprom 001b 8:7 reserved. yes yes 00b 9 prefetch early termination. values: 0 = terminates prefetching at the initial prefetch count if flow through is not achieved, and another prefetching read cycle is accepted by the pci 6150 1 = completes prefetching as programmed by the prefetch count registers, regardless of other outstanding prefetchable reads in the transaction queue yes yes; serial eeprom 0 10 read minimum enable. if set to 1, pci 6150 initiates read cycles only if there is sufficient space available in the fifo, as required by the prefetch count registers. yes yes; serial eeprom 0 11 reserved. yes no; serial eeprom 0 section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-22 ? 2005 plx technology, inc. all rights reserved. 12 memory write and invalidate control. values: 0 = retries memory write and invalidate commands if there is insufficient space for one cache line of data in the internal queues. 1 = passes memory write and invalidate commands if there are one or more cache lines of fifo space available. if there is insufficient space, completes as a memory write cycle. yes yes; serial eeprom 0 13 primary lock enable. if set to 1, pci 6150 follows the lock protocol on primary interface; otherwise, lock is ignored. yes yes; serial eeprom 1 14 secondary lock enable. if set to 1, pci 6150 follows the lock protocol on secondary in terface; otherwise, lock is ignored. yes yes; serial eeprom 1 15 reserved. yes no; serial eeprom 0 register 6-33. (mscopt; pci:46h) miscellaneous options (continued) bit description read write value after reset section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-23 6?registers 6.1.2.5 prefetch control registers 48h to 4eh are the flow-through prefetch control registers, which are used to fine-tune the pci 6150 memory read prefetch behavior. (refer to section 17, ?pci flow-through optimization,? for further details regarding these registers.) register 6-34. (pitlpcnt; pci:48h ) primary initial prefetch count bit description read write value after reset 5:0 primary initial prefetch count. controls the initial prefetch count on the primary bus dur ing reads to prefetchable memory space. value must be a power of two (only one bit should be set to 1 at any time). value is a number of dwords. bit 0 is read-only and always 0. yes yes [5:1]; serial eeprom 10h 7:6 reserved. returns 00b when read. yes no 00b register 6-35. (sitlpcnt; pci:49h) secondary initial prefetch count bit description read write value after reset 5:0 secondary initial prefetch count. controls the initial prefetch count on the secondary bus during reads to prefetchable memory space. value must be a power of two (only one bit should be set to 1 at any time). value is a number of dwords. bit 0 is read-only and always 0. yes yes [5:1]; serial eeprom 10h 7:6 reserved. returns 00b when read. yes no 00b section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-24 ? 2005 plx technology, inc. all rights reserved. register 6-36. (pincpcnt; pci:4ah) primary incremen tal prefetch count bit description read write value after reset 5:0 primary incremental prefetch count. controls the incremental read prefetch count. when an entry?s remaining prefetch dword count falls below this value, the bridge prefetches an additional ?p rimary incremental prefetch count? set of dwords. value must be a power of two (only one bit should be set to 1 at any time). value is a number of dwords. bit 0 is read-only and always 0. value must not exceed half the value programmed in the primary maximum prefetch count register (pmaxpcnt; pci:4ch). otherwise, no incremental prefetch is performed. yes yes [5:1]; serial eeprom 10h 7:6 reserved. returns 00b when read. yes no 00b register 6-37. (sincpcnt; pci:4bh) secondary incremental prefetch count bit description read write value after reset 5:0 secondary incremental prefetch count. controls the incremental read prefetch count. when an entry?s remaining prefetch dword count falls below this value, the bridge prefetches an additional ?secondary incremental prefetch count? set of dwords. value must be a power of two (only one bit should be set to 1 at any time). value is a number of dwords. bit 0 is read-only and always 0. value must not exceed half the value programmed in the secondary maximum prefetch count register (smaxpcnt; pci:4dh). otherwise, no increm ental prefetch is performed. yes yes [5:1]; serial eeprom 10h 7:6 reserved. returns 00b when read. yes no 00b section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-25 6?registers register 6-38. (pmaxpcnt; pci:4ch) primary maximum prefetch count bit description read write value after reset 5:0 primary maximum prefetch count. applies only to pci-to-pci bridging. limits the cumulative maximum count of prefetchable dwords allocat ed to one entry on the primary bus when flow through for that entry is not achieved. value must be an even number. bit 0 is read-only and always 0. value is specified in dwords, except if 0h value is programmed, which sets the primary maximum prefetch count to its maximum value of 256 bytes. a pci read cycle causes a pci request for the maximum count data. yes yes [5:1]; serial eeprom 20h 7:6 reserved. returns 00b when read. yes no 00b register 6-39. (smaxpcnt; pci:4dh) secondary maximum prefetch count bit description read write value after reset 5:0 secondary maximum prefetch count. applies only to pci-to-pci bridging. limits the cumulative maximum count of prefetchable dwords allocated to one entry on the secondary bus when flow through for that entry is not achieved. value must be an even number. bit 0 is read-only and always 0. value is specified in dwords, except if 0h value is programmed, which sets the secondary maximum prefetch count to its maximum value of 256 bytes. a pci read cycle causes a pci request for the maximum count data. yes yes [5:1]; serial eeprom 20h 7:6 reserved. returns 00b when read. yes no 00b section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-26 ? 2005 plx technology, inc. all rights reserved. register 6-40. (sftcr; pci:4eh) secondary flow-through control bit description read write value after reset 2:0 secondary posted write completion wait count. maximum number of clocks the pci 6150 waits for posted write data from the initiator if delivering write data in flow-through mode and the internal post write queues are almost empty. if the count is exceeded without additional data from the initiator, the cycle to the target is terminated and later completed. values: 000b = terminates the cycle if there is only one data entry remaining in the internal write queue 001b = de-asserts p_irdy# and waits one clock for source data on the secondary bus, before terminating cycle ? 111b = de-asserts p_irdy# and waits seven clocks for source data on the secondary bus, before terminating cycle yes yes; serial eeprom 111b 3 reserved. returns 00b when read. yes no 0 6:4 secondary delayed read completion wait count. maximum number of clocks the pci 6150 waits for delayed read data from the target, if returning read data in flow-through mode and the internal delayed read queue is almost full. if the count is exceeded without additional space in the queue, the cycle to target is terminated, and completed when the initiator retries the remainder of the cycle. values: 000b = terminates the cycle if there is only one data entry remaining in the read queue 001b = de-asserts p_trdy# and waits one clock for source data on the secondary bus, before terminating cycle ? 111b = de-asserts p_trdy# and waits seven clocks for source data on the secondary bus, before terminating cycle yes yes; serial eeprom 111b 7 reserved. returns 00b when read. yes no 0 section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-27 6?registers 6.1.2.6 internal arbiter control register 6-41. (iacntrl; pci:50h) internal arbiter control bit description read write value after reset 0 low-priority group fixed arbitration. if set to 1, the low-priority group uses fixed-pr iority arbitration; otherwise, rotating-priority arbitration is used. yes yes 0 1 low-priority group arbitration order. valid only when the low-priority arbitration group is set to a fixed arbitration scheme. values: 0 = priority decreases with bus master number. ( for example , assuming master 2 is set as the highest priority master, master 3 retains higher priority than master 4.) 1 = priority increases with bus master number. ( for example , assuming master 2 is set as the highest priority master, master 4 retains higher priority than master 3. this order is relative to the master with the highest priority for this group, as specified in iacntrl[7:4]. yes yes 0 2 high-priority group fixed arbitration. if set to 1, the high-priority group uses the fi xed-priority arbitration; otherwise, rotating-prior ity arbitration is used . yes yes 0 3 high-priority group arbitration order. valid only when the high-priority arbitration group is set to a fixed arbitration scheme. values: 0 = priority decreases with bus master number. ( for example , assuming master 2 is set as the highest priority master, master 3 retains higher priority than master 4.) 1 = priority increases with bus master number. ( for example, assuming master 2 is set as the highest priority master, master 4 retains higher priority than master 3.) this order is relative to the master with the highest priority for this group, as specified in iacntrl[11:8]. yes yes 0 7:4 highest priority master in low-priority group. controls which master in the low-priority group retain the highest priority. valid only if the group uses the fixed arbitration scheme. values: 0000b = master 0 retains highest priority 0001b = master 1 retains highest priority ? 1001b = pci 6150 retains highest priority 1010b ? 1111b = reserved yes yes 0000b section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-28 ? 2005 plx technology, inc. all rights reserved. 11:8 highest priority master in high-priority group. controls which master in the high-priority group retains the highest priority. valid only if the group uses the fixed arbitration scheme. values: 0000b = master 0 retains highest priority 0001b = master 1 retains highest priority ? 1001b = pci 6150 retains highest priority 1010b ? 1111b = reserved yes yes 0000b 15:12 bus grant parking control. controls bus grant behavior during idle. values: 0000b = last master granted is parked 0001b = master 0 is parked ? 1001b = master 8 is parked 1010b = pci 6150 is parked all other values de-assert the grant (no parking). yes yes 0000b register 6-41. (iacntrl; pci:50h) internal arbiter control (continued) bit description read write value after reset section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-29 6?registers 6.1.2.7 test and serial eeprom register 6-42. (test; pci:52h) test bit description read write value after reset 0 serial eeprom autoload control. if set to 1, disables serial eeprom autoload. for test use only. to stop serial eeprom load, write 1 to this bit within 1200 clocks after p_rstin# goes high. yes yes 0 1 fast serial eeprom autoload. if set to 1, speeds up serial eeprom autoload by 32 times. for test use only. to enable fast serial eeprom load, write 1 to this bit within 1200 clocks after p_rstin# goes high. yes yes 0 2 serial eeprom autoload status. serial eeprom autoload status is set to 1 during autoload. yes no serial eeprom autoload status 7:3 reserved. yes no 0h section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-30 ? 2005 plx technology, inc. all rights reserved. register 6-43. (eepcntrl; pci:54h) serial eeprom control bit description read write value after reset 0 start. starts serial eeprom read or write cycle. bit is cleared when serial eeprom load completes. yes yes 0 1 serial eeprom command. controls commands sent to the serial eeprom. values: 0 = read 1 = write yes yes 0 2 serial eeprom error. set to 1 if serial eeprom ack was not received during serial eeprom cycle. yes no ? 3 serial eeprom autoload successful. set to 1 if serial eeprom autoload successfully occurred after reset, with appropriate configuration registers loaded with the values programmed in the serial eeprom. if 0, the serial eeprom autoload was unsuccessful or disabled. yes no ? 5:4 reserved. returns 00b when read. yes no 00b 7:6 serial eeprom clock rate. controls the serial eeprom clock frequency. the serial eeprom clock is derived from the primary pci clock. values: 00 = pclk / 1024 (used for 66 mhz pci) 01 = pclk / 512 10 = pclk / 256 11 = pclk / 32 (test mode use only) yes yes 00b register 6-44. (eepaddr; pci:55h) serial eeprom address bit description read write value after reset 0 reserved . yes no ? 7:1 serial eeprom address. word address for the serial eeprom cycle. yes yes ? register 6-45. (eepdata; pci:56h) serial eeprom data bit description read write value after reset 15:0 serial eeprom data. contains data to be written to the serial eeprom. during reads, contains data received from the serial eeprom after a read cycle completes. yes yes ? section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-31 6?registers 6.1.2.8 primary system error event register 6-46. (pserred; pci:64h) p_serr# event disable bit description read write value after reset 0 reserved. yes no 0 1 posted write parity error. controls pci 6150 ability to assert p_serr# when a data parity error is detected on the target bus during a posted write transaction. p_serr# is asserted if this event occurs when bit is 0 and command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). yes yes 0 2 posted memory write non-delivery. controls pci 6150 ability to assert p_serr# when it is unable to deliver posted write data after 2 24 attempts [or programmed maximum retry count (tocntrl[2:0]; pci:45h)]. p_serr# is asserted if this event occurs when bit is 0 and command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). yes yes 0 3 target abort during posted write. controls pci 6150 ability to assert p_serr# when it receives a target abort while attempting to deliver posted write data. p_serr# is asserted if this event occurs when bit is 0 and command register p_serr# enable bit is set (pcicr[8]=1; pci:04h) yes yes 0 4 master abort on posted write. controls pci 6150 ability to assert p_serr# when it receives a master abort while attempting to deliver posted write data. p_serr# is asserted if this event occurs when bit is 0 and command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). yes yes 0 5 delayed configuration or i/o write non-delivery. controls pci 6150 ability to assert p_serr# when it is unable to deliver delayed write data after 2 24 attempts [or programmed maximum retry count (tocntrl[2:0]; pci:45h)]. p_serr# is asserted if this event occurs when bit is 0 and command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). yes yes 0 6 delayed read-no data from target. controls pci 6150 ability to assert p_serr# when it is unable to transfer read data from the target after 2 24 attempts [or programmed maximum retry count (tocntrl[2:0]; pci:45h)]. p_serr# is asserted if this event occurs when bit is 0 and command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). yes yes 0 7 reserved. returns 0 when read. yes no 0 section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-32 ? 2005 plx technology, inc. all rights reserved. 6.1.2.9 gpio register 6-47. (gpiood; pci:65h) gpio[3:0] output data bit description read write value after reset 3:0 gpio[3:0] output data write 1 to clear. writing 1 to these bits drives the corresponding signal low on the gpio[3:0] bus, if the signal is programmed as an output. writing 0 has no effect. read returns last written value. yes yes/set low 0h 7:4 gpio[3:0] output data write 1 to set. writing 1 to these bits drives the corresponding signal high on the gpio[3:0] bus, if the signal is programmed as an output. writing 0 has no effect. read returns last written value. yes yes/set high 0h register 6-48. (gpiooe; pc i:66h) gpio[3:0] output enable bit description read write value after reset 3:0 gpio[3:0] output enable write 1 to clear. writing 1 to these bits configures the corresponding signal on the gpio[3:0] bus as an input. writing 0 has no effect. read returns last written value. yes yes/set low 0h 7:4 gpio[3:0] output enable write 1 to set. writing 1 to these bits configures the corresponding signal on the gpio[3:0] bus as an output. writing 0 has no effect. read returns last written value. yes yes/set high 0h register 6-49. (gpioid; pci:67h) gpio[3:0] input data bit description read write value after reset 3:0 reserved. yes no 0h 7:4 gpio[3:0] input data. reads the gpio[3:0] pin state. the state is updated on the primary pci clock cycle, following a change in gpio[3:0] state. yes no ? section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-33 6?registers 6.1.2.10 secondary clock control register 6-50. (sclkcntrl; pc i:68h) secondary clock control bit description read write value after reset 1:0 clock 0 disable . if either bit is 0, s_clko0 is enabled. when both bits are 1, s_clko0 is disabled. upon secondary bus reset, shifting in a serial data stream initializes this bit. these bits are assigned to correspond to the philips 74f166 p_rsnt0[2:1]# slot 0 pins. yes yes 00b 3:2 clock 1 disable. if either bit is 0, s_clko1 is enabled. when both bits are 1, s_clko1 is disabled. upon secondary bus reset, shifting in a serial data stream initializes this bit. these bits are assigned to correspond to the philips 74f166 p_rsnt1[2:1]# slot 1 pins. yes yes 00b 5:4 clock 2 disable. if either bit is 0, s_clko2 is enabled. when both bits are 1, s_clko2 is disabled. upon secondary bus reset, shifting in a serial data stream initializes this bit. these bits are assigned to correspond to the philips 74f166 p_rsnt2[2:1]# slot 2 pins. yes yes 00b 7:6 clock 3 disable. if either bit is 0, s_clko3 is enabled. when both bits are 1, s_clko3 is disabled. upon secondary bus reset, shifting in a serial data stream initializes this bit. these bits are assigned to correspond to the philips 74f166 p_rsnt3[2:1]# slot 3 pins. yes yes 00b 8 clock 4 disable. if 0, s_clko4 is enabled. when 1, s_clko4 is disabled. upon secondary bus reset, shifting in a serial data stream initializes this bit. yes yes 0 9 clock 5 disable. if 0, s_clko5 is enabled. when 1, s_clko5 is disabled. upon secondary bus reset, shifting in a serial data stream initializes this bit. yes yes 0 10 clock 6 disable. if 0, s_clko6 is enabled. when 1, s_clko6 is disabled. upon secondary bus reset, shifting in a serial data stream initializes this bit. yes yes 0 11 clock 7 disable. if 0, s_clko7 is enabled. when 1, s_clko7 is disabled. upon secondary bus reset, shifting in a serial data stream initializes this bit. yes yes 0 12 clock 8 disable. if 0, s_clko8 is enabled. when 1, s_clko8 is disabled. upon secondary bus reset, shifting in a serial data stream initializes this bit. yes yes 0 13 clock 9 disable. if 0, s_clko9 is enabled. when 1, s_clko9 is disabled. upon secondary bus reset, shifting in a serial data stream initializes this bit. yes yes 0 15:14 reserved. yes no 00b section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-34 ? 2005 plx technology, inc. all rights reserved. 6.1.2.11 primary system error status register 6-51. (pserrsr; pci:6ah) p_serr# status bit description read write value after reset 0 address parity error. p_serr# is asserted because an address parity error occurred on either side of the bridge. yes yes/clr 0 1 posted write data parity error. p_serr# is asserted because a posted write data parity error occurred on the target bus. yes yes/clr 0 2 posted write non-delivery. p_serr# is asserted because pci 6150 was unable to deliver posted write data to the target before the timeout counter expired. yes yes/clr 0 3 target abort during posted write. p_serr# is asserted because pci 6150 received a tar get abort when delivering posted write data. yes yes/clr 0 4 master abort during posted write. p_serr# is asserted because pci 6150 received a mast er abort when delivering posted write data. yes yes/clr 0 5 delayed write non-delivery. p_serr# is asserted because pci 6150 was unable to deliver delayed write data before the timeout counter expired. yes yes/clr 0 6 delayed read failed. p_serr# is asserted because pci 6150 was unable to read data from the target before the timeout counter expired. yes yes/clr 0 7 delayed transaction master timeout. p_serr# is asserted because a master did not repeat a read or write transaction before the initiator bus master timeout counter expired. yes yes/clr 0 section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-35 6?registers 6.1.2.12 read-only register control register 6-52. (rrc; pci:9ch) read-only register control bit description read write value after reset 6:0 reserved. yes no 0h 7 read-only registers write enable. setting this bit to 1 enables writes to specific bits within these normally read-only registers (refer to the listed registers for further details): vendor and device ids (pciidr; pci:00h) pci class code (pciccr; pci:09h ? 0bh) pci header type (pcihtr; pci:0eh) pci built-in self-test (pcibistr; pci:0fh) power management capabilities (pmc; pci:deh) power management control/status (pmcsr; pci:e0h) power management data (pmcdata; pci:e3h) bit must be cleared after the values are modified in these read-only registers. yes yes 0 section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-36 ? 2005 plx technology, inc. all rights reserved. 6.1.2.13 power mana gement capability specific bits in the pmc; pci:deh, pmcdata; pci:e3h, and pmcsr; pci:e0h power management registers are normally read-only. however, their default values can be changed by firmware or software by setting the read-only registers write enable bit (rrc[7]=1; pci:9ch). after modifying these registers, the write enable bit must be cleared to preserve the read-only nature of these registers. it should be noted that the rrc[7] state does not affect write accesses to pmcsr[15, 8] . . register 6-53. (pmcapid; pci:dch) power management capability id bit description read write value after reset 7:0 power management capability id. pci-sig-issued capability id for power management is 1h. yes no 1h register 6-54. (pmnext; pci:ddh) powe r management next capability pointer bit description read write value after reset 7:0 next_cap pointer. provides an offset into pci configuration space for the hot swap capability location in the new capabilities linked list (e4h). yes no e4h section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-37 6?registers register 6-55. (pmc; pci:deh) power management capabilities bit description read write value after reset 2:0 version. set to 001b, which indicates that this function complies with pci power mgmt. r1.1 . yes only if rrc[7]=1; serial eeprom 001b 3 pme clock. set to 0, because pci 6150 does not support pme# signaling. yes only if rrc[7]=1; serial eeprom 0 4 auxiliary power source. set to 0, because pci 6150 does not support pme# signaling. yes only if rrc[7]=1; serial eeprom 0 5 device-specific initialization (dsi). returns 0, indicating pci 6150 does not require special initialization. yes only if rrc[7]=1; serial eeprom 0 8:6 reserved. yes no 000b 9 d 1 support. returns 1, indicating that pci 6150 supports the d 1 device power state. yes only if rrc[7]=1; serial eeprom 1 10 d 2 support. returns 1, indicating that pci 6150 supports the d 2 device power state. yes only if rrc[7]=1; serial eeprom 1 15:11 pme support. set to 0h, indicating that pme# is not supported. yes only if rrc[7]=1; serial eeprom 0h section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-38 ? 2005 plx technology, inc. all rights reserved. register 6-56. (pmcsr; pci:e0h) power management control/status bit description read write value after reset 1:0 power state. used to determine the current power state of a function and to set the function into a new power state. values: 00b = d 0 (default) 01b = d 1 ; valid only if pmc[9]=1; pci:82h 10b = d 2 ; valid only if pmc[10]=1; pci:82h 11b = d 3hot ; if bpcc_en=1, s_clko[9:0] are stopped yes yes; serial eeprom 00b 7:2 reserved. yes no 0h 8 pme enable. set to 0, because pci 6150 does not support pme# signaling. yes yes serial eeprom 0 12:9 data select. returns 0h, indicating pci 6150 does not return dynamic data. yes only if rrc[7]=1; serial eeprom 0h 14:13 data scale. returns 00b when read, as the pci 6150 does not return dynamic data. yes no; serial eeprom 00b 15 pme status. set to 0, because pci 6150 does not support pme# signaling. yes yes; serial eeprom 0 register 6-57. (pmcsr_bse; pci:e2h) pmcsr bridge supports extensions bit description read write value after reset 5:0 reserved. yes no 0h 6 b 2 /b 3 support for d 3hot . reflects bpcc_en input pin state. value of 1 indicates that when pci 6150 is programmed to d 3hot state, the secondary bus clock is stopped. yes no ? 7 bus power control enable. reflects bpcc_en input pin state. value of 1 indicates that the secondary bus power management state follows that of pci 6150, with one exception?d 3hot . yes no ? register 6-58. (pmcdata; pci:e3h) power management data bit description read write value after reset 7:0 power management data. used to report the state- dependent data requested by pmcsr[12:9]. value is scaled by the value reported by pmcsr[14:13]; pci:e0h. yes only if rrc[7]=1; serial eeprom 0h section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-39 6?registers 6.1.2.14 hot swap capability register 6-59. (hs_cntl; pci:e4h) hot swap control bit description read write value after reset 7:0 hot swap capability id. pci-sig-issued capability id for hot swap is 06h. yes no 06h register 6-60. (hs_next; pci:e5h) hot swap next capability pointer bit description read write value after reset 7:0 next_cap pointer. provides an offset into pci configuration space for the vpd capability location in the new capabilities linked list (e8h). yes no e8h register 6-61. (hs_csr; pci:e6h) hot swap control/status bit description read write value after reset 0 device hiding arm (dha). dha is set to 1 by hardware when the hot swap port pci rstin# becomes inactive and the handle switch remains unlocked. handle locking clears this bit. values: 0 = disarm device hiding 1 = arm device hiding yes yes 0 1 enum# mask status (eim). enables or disables enum# assertion. values: 0 = enables enum# assertion 1 = masks enum# assertion yes yes 0 2 pending insert or extract (pie). set when ins or ext is 1 or ins is armed (write 1 to ext bit). values: 0 = neither is pending 1 = in insertion or extraction is in progress yes no ? 3 led status (loo). indicates whether led is on or off. values: 0 = led off 1 = led on yes yes 0 5:4 programming interface (pi). hardcoded at 01b?ins, est, loo, eim, pie, and device hiding supported. upon rstin# assertion, the pci 6150 turns on the led. after rstin# de-assertion, the led remains on until the eject switch (handle) is closed, then the pci 6150 turns off the led. yes no 01b 6 extraction state (ext). set by hardware when the ejector handle is unlocked and ins=0. yes yes/clr ? 7 insertion state (ins). set by hardware when the hot swap port rstin# is de-asserted, serial eeprom autoload is completed, and ejector handle is locked. writing 1 to ext bit also arms ins. yes yes/clr ? 15:8 reserved. yes no 0h section 6 registers pci configuration register address mapping pci 6150bb data book, version 2.11 6-40 ? 2005 plx technology, inc. all rights reserved. 6.1.2.15 vpd capability register 6-62. (pvpdid; pci:e8h) vital product data capability id bit description read write value after reset 7:0 vital product data capability id. pci-sig-issued capability id for vpd is 03h. yes no 03h register 6-63. (pvpd_next; pci:e9h) vital product data next capability pointer bit description read write value after reset 7:0 next_cap pointer . provides offset into pci configuration space for the next capability location in the new capabilities linked list (00h). note: 00h indicates the end of the new capabilities linked list. yes no 00h register 6-64. (pvpdad; pci:eah) vital product data address bit description read write value after reset 1:0 reserved. yes no 00b 7:2 vpd address. offset into the serial eeprom to location where data is written and read. pci 6150 accesses the serial eeprom at address pvpdad[7:2]+40h. the 40h offset ensures that vpd accesses do not overwrite the pci 6150 serial eeprom configuration data stored in serial eeprom locations 00h to 3fh. yes yes 0 14:8 reserved. yes no 0h 15 vpd operation . writing 0 generates a read cycle from the serial eeprom at the vpd address specified in pvpdad[7:2]. this bit remains at logic 0 until the serial eeprom cycle is complete, at which time the bit is set to 1. data for reads is available in the vpd data register (pvpdata; pci:ech). writing 1 generates a write cycle to the serial eeprom at the vpd address specified in pvpdad[7:2]. remains at logic 1, until the serial eeprom cycle is completed, at which time the bit is cleared to 0. place data for writes into the vpd data register. yes yes 0 section 6 pci configuration register address mapping registers pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 6-41 6?registers register 6-65. (pvpdata; pci:ech) vpd data bit description read write value after reset 31:0 vpd data (serial eeprom data). the least significant byte of this register corresponds to the byte of vpd at the address specified by the vpd address register (pvpdad[7:2]; pci:a2h). data is read from or written to pvpdata, using standard configuration accesses. yes yes 0h pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 7-1 7?serial eeprom 7 serial eeprom this section describes information specific to the pci 6150 serial eeprom interface and use?access, autoload mode, and data structure. 7.1 overview important note: erroneous serial eeprom data can cause the pci 6150 to lock the system. provide an optional switch or jumper to disable the serial eeprom in board designs. the pci 6150 provides a two-wire interface to a serial eeprom device. the interface can control an issi is24c02 or compatible part, which is organized as 256 x 8 bits. the serial eeprom is used to initialize the internal pci 6150 registers, and alleviates the need for user software to configure the pci 6150. if a programmed serial eeprom is connected, the pci 6150 automatically loads data from the serial eeprom after p_rstin# de-assertion. the serial eeprom data structure is defined in section 7.4.1. the serial eeprom interface is organized on a 16-bit base in little endian format, and the pci 6150 supplies a 7-bit serial eeprom word address. the following pins are used for the serial eeprom interface: eepclk ?serial eeprom clock output eepdata ?serial eeprom bi-directional serial data ee_en#? low input enables serial eeprom access note: the pci 6150 does not control the serial eeprom a0 to a2 address inputs. it can only access serial eeprom addresses set to 0. 7.2 serial eeprom access the pci 6150 can access the serial eeprom on a word basis, using the hardware sequencer. users access one word data by way of the pci 6150 serial eeprom control register: serial eeprom start/read/write control (eepcntrl; pci:54h) serial eeprom address (eepaddr; pci:55h) serial eeprom data (eepdata; pci:56h) before each access, software should check the auto mode cycle in progress status (eepcntrl[0]; pci:54h, same bit as start) before issuing the next start. the following is the general procedure for read/ write serial eeprom accesses: 1. program the serial eeprom address register (eepaddr; pci:55h) with the word address. 2. writes ?program word data to the serial eeprom data register (eepdata; pci:56h). reads ?proceed to the next step. 3. writes ?set the serial eeprom command and start bits (eepcntrl[1:0]=11b; pci:54h, respectively) to start the serial eeprom sequencer. reads ?set the start bit (eepcntrl[1:0]=01b; pci:54h) to start the serial eeprom sequencer. 4. when the serial eeprom read/write is complete, as indicated by the bit value of 0 (serial eeprom control register, eepcntrl[0]=0; pci:54h): writes ?data was successfully written to the serial eeprom. reads ?data was loaded into the serial eeprom data register (eepdata; pci:56h) by the serial eeprom sequencer. section 7 serial eeprom serial eeprom autoload mode at reset pci 6150bb data book, version 2.11 7-2 ? 2005 plx technology, inc. all rights reserved. 7.3 serial eeprom autoload mode at reset upon p_rstin# going high at reset, the pci 6150 autoloads input for the serial eeprom autoload condition if ee_en#=0. the pci 6150 initially reads the first offset in the serial eeprom, which should contain a valid signature value of 1516h. if the signature is correct, register autoload immediately commences after reset. during autoload, the pci 6150 reads sequential words from the serial eeprom and writes to the appropriate registers. if a blank serial eeprom is connected, the pci 6150 stops loading the serial eeprom contents after reading the first word, as the serial eeprom?s signature is not valid. likewise, if no serial eeprom is connected, the pci 6150 also stops loading the serial eeprom contents after attempting to read the first word. before the pci 6150 registers can be accessed by way of the host, check the auto-load condition by reading the eepauto bit. host access is allowed only after the eepauto status becomes 0, which means that the auto load initialization sequence is complete. the serial eeprom initialized value is cleared by an active p_rstin# or power management-initiated internal reset. 7.4 serial eeprom data structure following reset and the previously described conditions, the pci 6150 autoloads the registers with serial eeprom data. figure 7-1 illustrates the serial eeprom data structure. the pci 6150 accesses the serial eeprom, one word at a time. it is important to note that in the data phase, bit orders are the reverse of that in the address phase. the pci 6150 supports only serial eeprom device address 0. figure 7-1. serial eeprom data structure a c k m s b m s b l s b l s b s t o p data (n) data (n +1) a c k a c k wor d address (n) m s b l s b 0 s t a r t 10 a c k w r i t e device address 10 0 00 10 a c k a c k wor d address (n) m s b l s b w r i t e device address 0 10 0 00 s t a r t 10 a c k r e a d device address 10 0 00 a c k m s b m s b l s b l s b data (n) data (n +1) n o a c k s t o p s t a r t read wr i t e section 7 serial eeprom data structure serial eeprom pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 7-3 7?serial eeprom 7.4.1 serial eeprom address and correspondi ng pci 6150 registers table 7-1. serial eeprom address and corresponding pci 6150 registers serial eeprom byte address pci configuration offset description 00h ? 01h ? serial eeprom signature. autoload proceeds only if it reads a value of 1516h on the first word loaded. value: 1516h = valid signature; otherwise, disables autoloading. 02h ? region enable. enables or disables certain regions of the pci configuration space from being loaded from the serial eeprom. valid combinations are: bit 0 = reserved. bits [4:1] = 0000b = stops autoload at serial eeprom offset 03h = group 1. 0001b = stops autoload at serial eeprom offset 13h = group 2. 0011b = stops autoload at serial eeprom offset 23h = group 3. 0111b, 1111b = reserved. other combinations are undefined. bits [7:5] = reserved. 03h ? enable miscellaneous functions. bit 0 = isa enable control bit write protect. when set, pci 6150 changes the standard pci-to-pci bridge control register (bcntrl[2]; pci:3eh) to read-only. the isa enable feature is then not available. bits [7:1] = reserved. end of group 1 04h ? 05h 00h ? 01h vendor id (pciidr[15:0]). 06h ? 07h 02h ? 03h device id (pciidr[31:16]). 08h ? reserved. 09h 09h class code. contains low byte of class code register (pciccr[7:0]). 0ah ? 0bh 0ah ? 0bh class code higher bytes. contains upper bytes of class code register (pciccr[23:8]). 0ch 0eh header type (pcihtr). 0dh 09h reserved. 0eh ? 0fh 0ah ? 0bh reserved. 10h 0eh reserved. 11h 0fh built-in self test (bist) (pcibistr). set to 0. 12h ? 13h 50h internal arbiter control (iacntrl). end of group 2 section 7 serial eeprom serial eeprom data structure pci 6150bb data book, version 2.11 7-4 ? 2005 plx technology, inc. all rights reserved. note: * these addresses will be defined in the next databook release. 14h 44h primary flow-through control (pftcr). 15h 45h timeout control (tocntrl). 16h ? 17h 46h ? 47h miscellaneous options (mscopt). 18h 48h primary initial prefetch count (pitlpcnt). 19h 49h secondary initial prefetch count (sitlpcnt). 1ah 4ah primary incremental prefetch count (pincpcnt). 1bh 4bh secondary incremental prefetch count (pincpcnt). 1ch 4ch primary maximum prefetch count (pmaxpcnt). 1dh 4dh secondary maximum prefetch count (pmaxpcnt). 1eh 4eh secondary flow-through control (sftcr). 1fh e3h power management data (pmcdata). 20h ? 21h e0h power management control/status (pmcsr). 22h ? 23h deh power management capabilities (pmc). end of group 3 26h ? 3fh ? reserved . must be set to 0. table 7-1. serial eeprom address and corresponding pci 6150 registers (continued) serial eeprom byte address pci configuration offset description pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 8-1 8?pci bus operation 8 pci bus operation this section describes pci transactions to which the pci 6150 responds and those it initiates when operating with one or both of its interfaces. 8.1 transactions table 8-1 lists the pci command codes and transaction types to which the pci 6150 responds and initiates. the master and target columns indicate support for transactions wherein the pci 6150 initiates transactions as a master, and responds to transactions as a target, on the primary and secondary buses. table 8-1. pci transactions cbe[3:0]# transaction type initiates as master responds as target primary secondary primary secondary 0000b interrupt acknowledge (not supported) nnnn 0001b special cycle (not supported) yynn 0010b i/o read y y y y 0011b i/o write y y y y 0100b reserved nnnn 0101b reserved nnnn 0110b memory read y y y y 0111b memory write y y y y 1000b reserved nnnn 1001b reserved nnnn 1010b configuration read n y y n 1011b configuration write type 1 y y type 1 1100b memory read multiple y y y y 1101b dual address cycle (dac) y y y y 1110b memory read line y y y y 1111b memory write and invalidate y y y y section 8 pci bus operation single address phase pci 6150bb data book, version 2.11 8-2 ? 2005 plx technology, inc. all rights reserved. as indicated in table 8-1, the pci 6150 does not support the following pci commands?it ignores them and reacts to these commands as follows: reserved ?the pci 6150 does not generate reserved command codes. interrupt acknowledge ?the pci 6150 never initiates an interrupt acknowledge transaction and, as a target, it ignores interrupt acknowledge transactions. interrupt acknowledge transactions are expected to reside entirely on the primary pci bus closest to the host bridge. special cycle ?the pci 6150 does not respond to special cycle transactions. to generate special cycle transactions on other pci buses (downstream or upstream), use a type 1 configuration command. type 0 configuration write ?the pci 6150 does not generate type 0 configuration write transactions on the primary interface. 8.2 single address phase the pci 6150 32-bit address uses a single address phase. this address is driven on ad[31:0], and the bus command is driven on p_cbe[3:0]#. the pci 6150 supports only the linear increment address mode, which is indicated when the lower two address bits equal 00b. if either of the lower two address bits is equal to a non-zero value, the pci 6150 automatically disconnects the transaction after the first data transfer. 8.3 dual address phase the pci 6150 supports the dual address cycle (dac) bus command to transfer 64-bit addresses. in dac transactions, the first address phase occurs during the initial frame# assertion, and the second address phase occurs one clock later. during the first address phase, the dac command is presented on cbe[3:0]#, and the lower 32 bits of the address on ad[31:0]. the second address phase retains the cycle command on cbe[3:0]#, and the upper 32 bits of the address on ad[31:0]. dacs are used to access locations that are not in the first 4 gb of pci memory space. addresses in the first 4 gb of pci memory space always use a single address cycle (sac). the pci 6150 supports dacs in the downstream and upstream directions. the pci 6150 responds to dacs for the following commands only: memory write memory write and invalidate memory read memory read line memory read multiple the pci 6150 forwards dacs downstream when their addresses fall within prefetchable memory space. dacs originating on the secondary bus, with addresses outside prefetchable memory space, are forwarded upstream. 8.4 device select (devsel#) generation the pci 6150 performs positive address decoding when accepting transactions on the primary or secondary bus. the pci 6150 never subtractively decodes. medium devsel# timing is used for 33 mhz operation. slow devsel# timing is used for 66 mhz operation. 8.5 data phase depending on the command type, the pci 6150 can support multiple data phase pci transactions. write transactions are treated as posted write or delayed write transactions. table 8-2 lists the forwarding method used for each type of write operation. table 8-2. write transaction forwarding transaction type forwarding method memory write posted memory write and invalidate i/o write delayed type 1 configuration write section 8 data phase pci bus operation pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 8-3 8?pci bus operation 8.5.1 posted write transactions when the pci 6150 determines that a memory write transaction is to be forwarded across the bridge, the pci 6150 asserts devsel# with slow timing and trdy# in the same cycle, provided that sufficient buffer space is available in the posted write data queue, and that the queue contains fewer than four outstanding posted transactions. the pci 6150 can accept one dual-dword of write data every pci clock cycle ( that is , no target wait states are inserted). up to 256 bytes of posted write data are stored in internal posted write buffers and eventually delivered to the target. the pci 6150 continues to accept write data until one of the following occurs: initiator normally terminates the transaction cache line boundary or an aligned 4-kb boundary is reached, depending on transaction type posted write data buffer fills when one of the last two events occurs, the pci 6150 returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. after the posted write transaction is selected for completion, the pci 6150 requests ownership of the target bus. this can occur while the pci 6150 is receiving data on the initiator bus. after the pci 6150 has ownership of the target bus, and the target bus is detected in the idle condition, the pci 6150 initiates the write cycle and continues to transfer write data until all write data corresponding to that transaction is delivered, or a target termination is received. if write data exists in the queue, the pci 6150 can drive one dual-dword of write data each pci clock cycle. if write data is flowing through the pci 6150 and the initiator stalls, the pci 6150 inserts wait states on the target bus if the queue empties. the pci 6150 ends the transaction on the target bus when one of the following conditions is met: all posted write data was delivered to the target target returns a target disconnect or retry (the pci 6150 starts another transaction to deliver the remaining write data) target returns a target abort (the pci 6150 discards remaining write data) the master latency timer expires, and the pci 6150 no longer retains the target bus grant (the pci 6150 starts another transaction to deliver the remaining write data). 8.5.2 memory write and invalidate transactions memory write and invalidate transactions guarantee the transfer of entire cache lines. by default, the pci 6150 retries a memory write and invalidate cycle until there is space for one or more cache lines of data in the internal buffers. the pci 6150 then completes the transaction on the secondary bus as a memory write and invalidate cycle. the pci 6150 can also be programmed to accept memory write and invalidate cycles under the same conditions as normal memory writes. in this case, if the write buffer fills before an entire cache line is transferred, the pci 6150 disconnects and completes the write cycle on the secondary bus as a normal memory write cycle by way of the miscellaneous options register memory write and invalidate control bit (mscopt[12]; pci:46h). the pci 6150 disconnects memory write and invalidate commands at aligned cache line boundaries. the cache line size register (pciclsr; pci:0ch) cache line size value provides the number of dwords in a cache line. for the pci 6150 to generate memory write and invalidate transactions, this cache line size value must be written to a value of 08h, 10h, or 20h dwords. if an invalid cache line size is programmed, wherein the value is 0, not a power of two, or greater than 20h dwords, the pci 6150 sets the cache line size to the minimum value of 08h. the pci 6150 always disconnects on the cache line boundary. when the memory write and invalidate transaction is disconnected before a cache line boundary is reached (typically because the posted write data buffer fills), the transaction is converted to a memory write transaction. section 8 pci bus operation data phase pci 6150bb data book, version 2.11 8-4 ? 2005 plx technology, inc. all rights reserved. 8.5.3 delayed write transactions a delayed write transaction forwards i/o write and type 1 configuration cycles by way of the pci 6150, and is limited to a single dword data transfer. when a write transaction is first detected on the initiator bus, the pci 6150 claims the access and returns a target retry to the initiator. during the cycle, the pci 6150 samples the bus command, address, and address parity bits. the pci 6150 also samples the first data dword, byte enable bits, and data parity. cycle information is placed into the delayed transaction queue if there are no other existing delayed transactions with the same cycle information, and if the delayed transaction queue is not full. when the pci 6150 schedules a delayed write transaction to be the next cycle to complete based on its ordering constraints, the pci 6150 initiates the transaction on the target bus. the pci 6150 transfers the write data to the target. if the pci 6150 receives a target retry in response to the write transaction on the target bus, the pci 6150 continues to repeat the write transaction until the data transfer is complete, or an error condition is encountered. if the pci 6150 is unable to deliver write data after 2 24 attempts (programmable through the timeout control register maximum retry counter control bits, tocntrl[2:0]; pci:45h), the pci 6150 ceases further write attempts and returns a target abort to the initiator. the delayed transaction is removed from the delayed transaction queue. the pci 6150 also asserts p_serr# if the command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). when the initiator repeats the same write transaction (same command, address, byte enable bits, and data), after the pci 6150 has completed data delivery and retains all complete cycle information in the queue, the pci 6150 claims the access and returns trdy# to the initiator, indicating that the write data was transferred. if the initiator requests multiple dwords, the pci 6150 asserts stop#, in conjunction with trdy#, to signal a target disconnect. only those bytes of write data with valid byte enable bits are compared. if any byte enable bits are disabled (driven high), the corresponding byte of write data is not compared. if the initiator repeats the write transaction before the data is transferred to the target, the pci 6150 returns a target retry to the initiator. the pci 6150 continues to return a target retry to the initiator until write data is delivered to the target or an error condition is encountered. when the write transaction is repeated, the pci 6150 does not make a new entry into the delayed transaction queue. the pci 6150 implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction queue. the initial value of this timer can be set to one of four values, selectable through the primary and secondary bridge control register master timeout bits (bcntrl[8:9]; pci:3eh, respectively), as well as the timeout control register master timeout divider bits (tocntrl[7:4]; pci:45h). if the discard timer expires before the write cycle is retried, the pci 6150 discards the delayed write transaction from the delayed transaction queue. the pci 6150 also conditionally asserts p_serr#. section 8 data phase pci bus operation pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 8-5 8?pci bus operation 8.5.4 write transaction address boundaries the pci 6150 imposes internal address boundaries when accepting write data. the aligned address boundaries are used to prevent the pci 6150 from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. when the aligned address boundaries are reached (per conditions listed in table 8-3), the pci 6150 returns a target disconnect to the initiator. 8.5.5 buffering multiple write transactions the pci 6150 continues to accept posted memory write transactions if space for at least 1 dword of data in the posted write data buffer remains and there are fewer than four outstanding posted memory write cycles. if the posted write data buffer fills before the initiator terminates the write transaction, the pci 6150 returns a target disconnect to the initiator. delayed write transactions are posted when one or more open entries exist in the delayed transaction queue. the pci 6150 can queue up to four posted write transactions and four delayed transactions in both the downstream and upstream directions. 8.5.6 read transactions delayed read forwarding is used for all read transactions that cross the pci 6150. delayed read transactions are treated as prefetchable or non-prefetchable. table 8-4 delineates the read behavior (prefetchable or non-prefetchable) for each type of read operation. table 8-3. write transaction disconnect address boundaries transaction type condition aligned address boundary delayed write all disconnects after one data transfer posted memory write memory write disconnect control bit = 0 1 4-kb aligned address boundary memory write disconnect control bit = 1 1 1. memory write disconnect control bit is located in the chip control register in configuration space (ccntrl[1]; pci:40h). disconnects at cache line boundary posted memory write and invalidate cache line size = 8h 8h-dword aligned address boundary cache line size = 10h 10h-dword aligned address boundary cache line size = 12h 12h-dword aligned address boundary table 8-4. read transaction prefetching transaction type read behavior i/o read never prefetches configuration read memory read downstream?prefetches if address is in prefetchable space upstream?prefetches if prefetch disable is off (default) memory read line always prefetches if request is for more than one data transfer memory read multiple section 8 pci bus operation data phase pci 6150bb data book, version 2.11 8-6 ? 2005 plx technology, inc. all rights reserved. 8.5.7 prefetchable read transactions a prefetchable read transaction is a read transaction wherein the pci 6150 performs speculative dword reads, transferring data from the target before the initiator requests the data. this behavior allows a prefetchable read transaction to consist of multiple data transfers. only the first byte enable bits can be forwarded. the pci 6150 enables all byte enable bits of subsequent transfers. prefetchable behavior is used for memory read line and memory read multiple transactions, as well as memory read transactions that fall into prefetchable memory space. the amount of prefetched data depends on the transaction type. the amount of prefetching may also be affected by the amount of free space in the pci 6150 read fifo and by the read address boundaries encountered. in addition, there are several pci 6150-specific registers that can be used to optimize read prefetch behavior. prefetching should not be used for those read transactions that cause side effects on the target device ( that is , control and status registers, fifos, and so forth). the target device bars indicate whether a memory address region is prefetchable. 8.5.8 non-prefetchable read transactions a non-prefetchable read transaction is a read transaction issued by the initiator into a non- prefetchable region. the transaction is used for i/o and configuration read transactions, as well as for memory reads from non-prefetchable memory space. in this case, the pci 6150 requests only 1 dword from the target and disconnects the initiator after delivery of the first dword of read data. use non-prefetchable read transactions for regions in which extra read transactions could have side effects ( such as in fifo memory or the control registers). if it is important to retain the byte enable bit values during the data phase of cycles forwarded across the bridge, use non-prefetchable read transactions. if these locations are mapped into memory space, use the memory read command and map the target into non-prefetchable (memory- mapped i/o) memory space to utilize non-prefetching behavior. 8.5.9 read prefetch address boundaries the pci 6150 imposes internal read address boundaries on read prefetching. the pci 6150 uses the address boundary to calculate the initial amount of prefetched data. during read transactions to prefetchable regions, the pci 6150 prefetches data until it reaches one of these aligned address boundaries, unless the target signals a target disconnect before reaching the read prefetch boundary. after reaching the aligned address boundary, the pci 6150 may optionally continue prefetching data, depending on certain conditions. (refer to section 17, ?pci flow-through optimization.?) when finished transferring read data to the initiator, the pci 6150 returns a target disconnect with the last data transfer, unless the initiator completes the transaction before delivering all the prefetched read data. remaining prefetched data is discarded. prefetchable read transactions in flow-through mode prefetch to the nearest aligned 4-kb address boundary, or until the initiator de-asserts frame#. table 8-5 delineates the read prefetch address boundaries for read transactions during non-flow- through mode. table 8-5. read prefetch address boundaries transaction type address space prefetch aligned address boundary configuration read ? 1 dword (no prefetch) i/o read memory read non-prefetchable memory read prefetchable configured by way of prefetch count registers memory read line memory read multiple section 8 data phase pci bus operation pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 8-7 8?pci bus operation 8.5.10 delayed read requests the pci 6150 treats all read transactions as delayed read transactions ( that is , the read request from the initiator is posted into a delayed transaction queue). read data from the target is placed into the read data queue directed toward the initiator bus interface and transferred to the initiator when the initiator repeats the read transaction. when the pci 6150 accepts a delayed read request, it first samples the read address, read bus command, and address parity. when irdy# is asserted, the pci 6150 samples the byte enable bits for the first data phase. this information is entered into the delayed transaction queue. the pci 6150 terminates the transaction by signaling a target retry to the initiator. upon receiving the target retry, the initiator must to continue to repeat the same read transaction until at least one data transfer completes, or until it receives a target response other than a target retry (master or target abort). 8.5.11 delayed read completion with target when a delayed read request is scheduled to be executed, the pci 6150 arbitrates for the target bus and initiates the read transaction, using the exact read address and read command captured from the initiator during the initial delayed read request. if the read transaction is non-prefetchable, the pci 6150 drives the captured byte enable bits during the next cycle. if the transaction is a prefetchable read transaction, the pci 6150 drives the captured (first) byte enable bits, followed by 0 for the subsequent data phases. if the pci 6150 receives a target retry in response to the read transaction on the target bus, it repeats the read transaction until at least one data transfer completes or it encounters an error condition. if the transaction is terminated by way of a normal master termination or target disconnect after at least one data transfer is complete, the pci 6150 does not initiate further attempts to read additional data. if the pci 6150 is unable to obtain read data from the target after 2 24 attempts (default), the pci 6150 ceases further read attempts and returns a target abort to the initiator. the delayed transaction is removed from the delayed transaction queue. the pci 6150 also asserts p_serr# if the command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). after receiving devsel# and trdy# from the target, the pci 6150 transfers the data stored in the internal read fifo, then terminates the transaction. the pci 6150 can accept 1 dword/qword of read data during each pci clock cycle?no master wait states are inserted. the number of dwords/qwords transferred during a delayed read transaction depends on the conditions delineated in table 8-5 (assuming no target disconnect is received). 8.5.12 delayed read completion on initiator bus when the delayed read transaction completes on the target bus, the delayed read data is at the head of the read data queue. when all ordering constraints with posted write transactions are satisfied, the pci 6150 transfers the data to the initiator when the initiator repeats the transaction. for memory read transactions, the pci 6150 aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. the pci 6150 returns a target disconnect along with the transfer of the last dword of read data to the initiator. if the pci 6150 initiator terminates the transaction before all read data is transferred, the remaining read data in the data buffers is discarded. when the master repeats the transaction and starts transferring prefetchable read data from the data buffers while the read transaction on the target bus is in progress, and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. because data is flowing from the target to the initiator through the data buffers, long read bursts can be sustained. in this case, the read transaction is allowed to continue until the initiator terminates the transaction, an aligned 4-kb address boundary is reached, or the buffer fills, whichever occurs first. when the buffer empties, the pci 6150 reflects the stalled condition to the initiator by de-asserting trdy# for a maximum of eight clock periods until more read data is available; otherwise, the pci 6150 disconnects the cycle. when the initiator terminates the transaction, the pci 6150 de-assertion section 8 pci bus operation data phase pci 6150bb data book, version 2.11 8-8 ? 2005 plx technology, inc. all rights reserved. of frame# on the initiator bus is forwarded to the target bus. any remaining read data is discarded. the pci 6150 implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction queue. the initial value of this timer can be set to one of four values, selectable through the primary and secondary bridge control register master timeout bits (bcntrl[8:9]; pci:3eh, respectively), as well as the timeout control register master timeout divider bits (tocntrl[7:4]; pci:45h). if the discard timer expires before the write cycle is retried, the pci 6150 discards the delayed write transaction from the delayed transaction queue. the pci 6150 also conditionally asserts p_serr#. the pci 6150 has the capability to post multiple delayed read requests, up to a maximum of four in both directions. if an initiator starts a read transaction that matches the address and read command of a queued read transaction, the current read command is not stored because it is contained in the delayed transaction queue. 8.5.13 configuration transactions configuration transactions are used to initialize a pci system. every pci device has a configuration space that is accessed by configuration commands. all registers are accessible only in configuration space. in addition to accepting configuration transactions for initialization of its own configuration space, the pci 6150 forwards configuration transactions for device initialization in hierarchical pci bus systems, as well as special cycle generation. to support hierarchical pci bus systems, type 0 and type 1 configuration transactions are specified. type 0 configuration transactions are issued when the intended target resides on the same pci bus as the initiator. type 0 configuration transactions are identified by the configuration command and the lowest two bits of the address are set to 00b. type 1 configuration transactions are issued when the intended target resides on another pci bus, or a special cycle is to be generated on another pci bus. type 1 configuration commands are identified by the configuration command and the lowest two address bits are set to 01b. the register number is found in both type 0 and type 1 formats and provides the dword address of the configuration register to be accessed. the function number is also included in both type 0 and type 1 formats, and indicates which function of a multi-function device is to be accessed. for single-function devices, this value is not decoded. type 1 configuration transaction addresses also include five bits, designating the device number that identifies the target pci bus device to be accessed. in addition, the bus number in type 1 transactions specifies the target pci bus. 8.5.14 pci 6150 type 0 access configuration space is accessed by a type 0 configuration transaction on the primary interface. configuration space is not accessible from the secondary bus. the pci 6150 responds to a type 0 configuration transaction by asserting p_devsel# when the following conditions are met during the address phase: bus command is a configuration read or write transaction. lower two address bits on p_ad[1:0] must be 01b. p_idsel must be asserted. pci 6150 limits all configuration accesses to a single dword data transfer and returns a target disconnect with the first data transfer if additional data phases are requested. because read transactions to configuration space do not have side effects, all bytes in the requested dword are returned, regardless of the byte enable bit values. type 0 configuration read and write transactions do not use data buffers ( that is , these transactions are immediately completed, regardless of the data buffers state). the pci 6150 ignores all type 0 transactions initiated on the secondary interface. section 8 data phase pci bus operation pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 8-9 8?pci bus operation 8.5.15 type 1-to-type 0 translation type 1 configuration transactions are specifically used for device configuration in a hierarchical pci bus system. a pci-to-pci bridge is the only type of device that should respond to a type 1 configuration command. type 1 configuration commands are used when the configuration access is intended for a pci device that resides on a pci bus other than the one where the type 1 transaction is generated. the pci 6150 performs a type 1-to-type 0 translation when the type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. the pci 6150 must convert the configuration command to a type 0 format, enabling the secondary bus device to respond to the command. type 1-to-type 0 translations are performed only in the downstream direction ( that is , the pci 6150 generates a type 0 transaction only on the secondary bus, and never on the primary bus). the pci 6150 responds to a type 1 configuration transaction and translates the transaction into a type 0 transaction on the secondary bus when the following conditions are met during the address phase: lower two address bits on p_ad[1:0] are 01b bus number in address field p_ad[23:16] is equal to the secondary bus number register value in configuration space (pcisbno; pci:19h) bus command on p_cbe[3:0]# is a configuration read or write transaction when translating a type 1 transaction to a type 0 transaction on the secondary interface, the pci 6150 performs the following translations to the address: sets the lower two address bits on s_ad[1:0] to 00b decodes the device number and drives the bit pattern specified in table 8-6 on s_ad[31:16] for the purpose of asserting the device?s idsel signal sets s_ad[15:11] to 0h leaves the function and register number fields unchanged the pci 6150 asserts unique address lines, based on the device number. these address lines may be used as secondary idsel signals. address line mapping depends on the device number in the type 1 address bits, p_ad[15:11]. the pci 6150 uses the mapping presented in table 8-6. the pci 6150 can assert up to 16 unique address lines to be used as secondary idsel signals for up to 16 secondary bus devices, for device numbers ranging from 0 to 15. because of the pci bus electrical loading constraints, more than 16 idsel signals should not be necessary. however, if more than 15 device numbers are needed, an external method of generating idsel lines must be used, and the upper address bits are not asserted. the configuration transaction is translated and passed from primary-to-secondary bus. if an idsel pin is not asserted to a secondary device, the transaction terminates in a master abort. the pci 6150 forwards type 1-to-type 0 configuration read or write transactions as delayed transactions. type 1-to-type 0 configuration read or write transactions are limited to a single 32-bit data transfer. when type 1-to-type 0 configuration cycles are forwarded, address stepping is used, and a valid address is driven on the bus before frame# assertion. type 0 configuration address stepping is programmable through the miscellaneous options register address step control bits (mscopt[6:4]; pci:46h). section 8 pci bus operation data phase pci 6150bb data book, version 2.11 8-10 ? 2005 plx technology, inc. all rights reserved. table 8-6. device number to idsel s_ad pin mapping device number p_ad[15:11] secondary idsel s_ad[31:16] s_ad bit 0h 00000b 0000_0000_0000_0001b 16 1h 00001b 0000_0000_0000_0010b 17 2h 00010b 0000_0000_0000_0100b 18 3h 00011b 0000_0000_0000_1000b 19 4h 00100b 0000_0000_0001_0000b 20 5h 00101b 0000_0000_0010_0000b 21 6h 00110b 0000_0000_0100_0000b 22 7h 00111b 0000_0000_1000_0000b 23 8h 01000b 0000_0001_0000_0000b 24 9h 01001b 0000_0010_0000_0000b 25 10h 01010b 0000_0100_0000_0000b 26 11h 01011b 0000_1000_0000_0000b 27 12h 01100b 0001_0000_0000_0000b 28 13h 01101b 0010_0000_0000_0000b 29 14h 01110b 0100_0000_0000_0000b 30 15h 01111b 1000_0000_0000_0000b 31 special cycle 1xxxxb 0000_0000_0000_0000b ? section 8 data phase pci bus operation pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 8-11 8?pci bus operation 8.5.16 type 1-to-type 1 forwarding type 1-to-type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of pci-to-pci bridges are used. when the pci 6150 detects a type 1 configuration transaction intended for a pci bus downstream from the secondary bus, the pci 6150 forwards the transaction unchanged to the secondary bus. ultimately, this transaction is translated to a type 0 configuration command or to a special cycle transaction by a downstream pci-to-pci bridge. downstream type 1-to-type 1 forwarding occurs when the following conditions are met during the address phase: lower two address bits on ad[1:0] are equal to 01b bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register (pcisbno; pci:19h) and upper limit (inclusive) in the subordinate bus number register (pcisubno; pci:1ah) bus command is a configuration read or write transaction the pci 6150 also supports type 1-to-type 1 upstream configuration write transaction forwarding to support upstream special cycle generation. a type 1 configuration command is forwarded upstream when the following conditions are met: lower two address bits on ad[1:0] are equal to 01b bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register (pcisbno; pci:19h) and upper limit (inclusive) in the subordinate bus number register (pcisubno; pci:1ah) device number in address bits ad[15:11] is equal to 11111b function number in address bits ad[10:8] is equal to 111b bus command is a configuration write transaction pci 6150 forwards type 1-to-type 1 configuration write transactions as delayed transactions, limited to a single data transfer 8.5.17 special cycles the type 1 configuration mechanism is used to generate special cycle transactions in hierarchical pci systems. special cycle transactions are ignored by operating as a target and are not forwarded across the bridge. special cycle transactions can be generated from type 1 configuration write transactions in the downstream or upstream direction. the pci 6150 initiates a special cycle on the target bus when a type 1 configuration write transaction is detected on the initiating bus and the following conditions are met during the address phase: lower two address bits on ad[1:0] are equal to 01b device number in address bits ad[15:11] is equal to 11111b function number in address bits ad[10:8] is equal to 111b register number in address bits ad[7:2] is equal to 0h bus number is equal to the secondary bus number register value in configuration space (pcisbno; pci:19h) for downstream forwarding, or equal to the primary bus number register value in configuration space (pcipbno; pci:18h) for upstream forwarding bus command on the initiator cbe bus is a configuration write command when the pci 6150 initiates a transaction on the target interface, the bus command is changed from configuration write to special cycle. the address and data are forwarded, unchanged. devices that use special cycle ignore the address and decode only the bus command. the data phase contains the special cycle message. the transaction is forwarded as a delayed transaction because special cycles complete as master aborts. after the transaction is completed on the target bus, through master abort condition detection, the pci 6150 responds with trdy# to the next attempt of the configuration transaction from the initiator. if more than one data transfer is requested, the pci 6150 responds with a target disconnect operation during the first data phase. section 8 pci bus operation transaction termination pci 6150bb data book, version 2.11 8-12 ? 2005 plx technology, inc. all rights reserved. 8.6 transaction termination this subsection describes how the pci 6150 returns transaction termination conditions to the initiator. the initiator can terminate transactions with one of the following types of termination: normal termination ?occurs when the initiator de-asserts frame# at the beginning of the last data phase, and de-asserts irdy# at the end of the last data phase in conjunction with trdy# or stop# assertion from the target. master abort ?occurs when no target response is detected. when the initiator does not detect the devsel# signal from the target within five clock cycles after asserting frame#, the initiator terminates the transaction with a master abort. if frame# is asserted, the initiator de-asserts frame# on the next cycle, then de-asserts irdy# on the following cycle. irdy# must be asserted in the same cycle in which frame# is de-asserted. if frame# was de-asserted, irdy# can be de-asserted on the next clock cycle following master abort condition detection. the target can terminate transactions with one of the following types of termination: normal termination ?trdy# and devsel# are asserted in conjunction with frame# de-assertion and irdy# assertion. target retry ?stop# and devsel# are asserted without trdy# during the first data phase. no data transfers during the transaction. this transaction must be repeated. target disconnect (with data transfer) ? devsel# and stop# are asserted with trdy#. indicates that this is the last data transfer of the transaction. target disconnect (without data transfer) ? stop# and devsel# are asserted without trdy# after previous data transfers. indicates that no further data transfers are made during this transaction. target abort ?stop# is asserted without devsel# and trdy#. indicates that the target is never able to complete this transaction. devsel# must be asserted for at least one cycle during the transaction before the target abort is signaled. 8.6.1 pci 6150-initiated master termination as an initiator, the pci 6150 uses normal termination if devsel# is returned by the target within five clock cycles of pci 6150 frame# assertion on the target bus. in this case, the pci 6150 terminates a transaction when the following conditions are met: during delayed write transactions, a single dword/ qword is delivered. during non-prefetchable read transactions, a single dword/qword is transferred from the target. during prefetchable read transactions, a prefetch boundary is reached. for posted write transactions, all write data for the transaction is transferred from data buffers to the target. for burst transfers ( except memory write and invalidate transactions), the master latency timer expires and the pci 6150 bus grant is de-asserted. target terminates the transaction with a retry, disconnect, or target abort. if the pci 6150 is delivering posted write data when it terminates the transaction because the master latency timer expired, the pci 6150 initiates another transaction to deliver the remaining write data. the transaction address is updated to reflect the address of the current dword to be delivered. if the pci 6150 is delivering posted write data when it terminates the transaction because the master latency timer expires, the pci 6150 initiates another transaction to deliver the remaining write data. the transaction address is updated to reflect the current dword address to be delivered. if the pci 6150 is prefetching read data when it terminates the transaction because the master latency timer expired, the pci 6150 does not repeat the transaction to obtain additional data. section 8 transaction termination pci bus operation pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 8-13 8?pci bus operation 8.6.2 master abort received by pci 6150 if the initiator initiates a transaction on the target bus and does not detect devsel# returned by the target within five clock cycles of frame# assertion, the pci 6150 terminates the transaction, as specified in the bridge control register master abort mode bit (bcntrl[5]; pci:3eh). for delayed read and write transactions, the pci 6150 can assert trdy# and return ffff_ffffh for reads, or return a target abort. serr# is also optionally asserted. when a master abort is received in response to a posted write transaction, the pci 6150 discards the posted write data and makes no further attempts to deliver the data. the pci 6150 sets the status register received master abort bit when the master abort is received on the primary bus (pcisr[13]=1; pci:06h), or the secondary status register received master abort bit when the master abort is received on the secondary interface (pcissr[13]=1; pci:1eh). when the master abort mode bit is set and a master abort is detected in response to a posted write transaction, the pci 6150 also asserts p_serr#, if enabled (pcicr[8]=1; pci:04h), but not disabled by the device-specific p_serr# disable for master aborts that occur during posted write transactions. (refer to table 8-7.) 8.6.3 target termination received by pci 6150 when the pci 6150 initiates a transaction on the target bus and the target responds with devsel#, the target can end the transaction with one of the following types of termination: normal termination (upon frame# de-assertion) target retry target disconnect target abort the pci 6150 controls these terminations using various methods, depending on the type of transaction performed. table 8-7. p_serr# assertion requirements in response to master abort on posted write description bit received master abort pcisr[13]=1; pci:06h p_serr# enable pcicr[8]=1; pci:04h master abort on posted write pserred[4]=0; pci:64h section 8 pci bus operation transaction termination pci 6150bb data book, version 2.11 8-14 ? 2005 plx technology, inc. all rights reserved. 8.6.3.1 posted write target termination response when the pci 6150 initiates a posted write transaction, the target termination cannot be returned to the initiator. table 8-8 delineates the response to each type of target termination that occurs during a posted write transaction. when a target retry or disconnect is returned and posted write data associated with that transaction remains in the write buffers, the pci 6150 initiates another write transaction to attempt to deliver the remaining write data. in the case of a target retry, the same address is driven as for the initial write transaction attempt. if a target disconnect is received, the address that is driven on a subsequent write transaction attempt is updated to reflect the current dword address. if the initial write transaction is a memory write and invalidate transaction, and a partial delivery of write data to the target is performed before a target disconnect is received, the pci 6150 uses the memory write command to deliver the remaining write data because less than a cache line is transferred in the subsequent write transaction attempt. after the pci 6150 makes 2 24 write attempts and fails to deliver all posted write data associated with that transaction, the pci 6150 asserts p_serr#, if enabled in the command register, and the device-specific p_serr# disable bit for this condition is not set. (refer to table 8-9.) the write data is discarded. table 8-8. response to post ed write target termination target termination response normal no additional action. target retry repeats write transaction to target. target disconnect initiates write transaction to deliver remaining posted write data. target abort sets target interface status register received tar get abort bit (primary?pcisr[12]=1, pci:06h, secondary? pcissr[12]=1; pci:1eh). asserts p_serr#, if enabled, and sets the primary status register signaled system error bit (pcicr[8]=1; pci:04h and pcisr[14]=1; pci:06h, respectively). table 8-9. p_serr# assertion requirements in response to posted write parity error description bit p_serr# enable pcicr[8]=0; pci:04h posted write parity error pserred[1]=0; pci:64h section 8 transaction termination pci bus operation pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 8-15 8?pci bus operation 8.6.3.2 delayed write target termination response when the pci 6150 initiates a delayed write transaction, the type of target termination received from the target can be returned to the initiator. table 8-10 delineates the response to each type of target termination that occurs during a delayed write transaction. the pci 6150 repeats a delayed write transaction until the pci 6150: completes at least one data transfer receives a master abort receives a target abort the pci 6150 makes 2 24 write attempts (default), resulting in a response of target retry. after the pci 6150 makes 2 24 attempts of the same delayed write transaction on the target bus, the pci 6150 asserts p_serr# if the command register p_serr# enable bit is set and the implementation-specific p_serr# disable bit for this condition is not set. (refer to table 8-11.) the pci 6150 stops initiating transactions in response to that delayed write transaction and the delayed write request is discarded. upon a subsequent write transaction attempt by the initiator, the pci 6150 returns a target abort. table 8-10. response to delayed write target termination target termination response normal returns disconnect to initiator with first data transfer only if multiple data phases are requested. target retry returns target retry to initiator. continue write attempts to target. target disconnect returns disconnec t to initiator with first data transfer only if multiple data phases are requested. target abort returns target abort to initiator. sets target interface status r egister received target abort bit. sets initiator interface status register signaled target abort bit. initiator (primary bus) target (secondary bus) initiator (secondary bus) target (primary bus) pcisr[11]=1; pci:06h pcissr[12]=1; pci:1eh pcisr[12]=1; pci:06h pcissr[11]=1; pci:1eh table 8-11. p_serr# assertion requirements in response to delayed write description bit p_serr# enable pcicr[8]=1; pci:04h delayed configuration or i/o write non-delivery pserred[5]=0; pci:64h section 8 pci bus operation transaction termination pci 6150bb data book, version 2.11 8-16 ? 2005 plx technology, inc. all rights reserved. 8.6.3.3 delayed read target termination response when the pci 6150 initiates a delayed read transaction, the abnormal target responses can be returned to the initiator. other target responses depend on the amount of data the initiator requests. table 8-12 delineates the response to each type of target termination that occurs during a delayed read transaction. the pci 6150 repeats a delayed read transaction until the pci 6150: completes at least one data transfer receives a master abort receives a target abort produces 2 24 read attempts, resulting in a response of target retry after the pci 6150 produces 2 24 attempts of the same delayed read transaction on the target bus, the pci 6150 asserts p_serr# if the command register p_serr# enable bit is set and the implementation- specific p_serr# disable bit for this condition is not set. (refer to table 8-13.) the pci 6150 stops initiating transactions in response to that delayed read transaction, and the delayed read request is discarded. upon a subsequent read transaction attempt by the initiator, the pci 6150 returns a target abort. table 8-12. response to delayed read target termination target termination response normal if prefetchable, target disconnects only if initiator reques ts more data than read from target. if non-prefetchable, target disconnects on first data phase. target retry re-initiates read transaction to target. target disconnect if initiator requests more data than read from target, returns target disconnect to initiator. target abort returns target abort to initiator. sets target interface status register received target abort bit. sets initiator interface status register signaled target abort bit. initiator (primary bus) target (secondary bus) initiator (secondary bus) target (primary bus) pcisr[11]=1; pci:06h pcissr[12]=1; pci:1eh pcisr[12]=1; pci:06h pcissr[11]=1; pci:1eh table 8-13. p_serr# assertion requirements in response to delayed read description bit p_serr# enable pcicr[8]=1; pci:04h delayed read-no data from target pserred[6]=0; pci:64h section 8 transaction termination pci bus operation pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 8-17 8?pci bus operation 8.6.4 pci 6150-initiated target termination the pci 6150 can return a target retry, disconnect, or abort to an initiator for reasons other than detection of that condition at the target interface. 8.6.4.1 target retry when it cannot accept write data or return read data as a result of internal conditions, the pci 6150 returns a target retry to the initiator when any of the following conditions are met: delayed write transactions transaction is in the process of entering the delayed transaction queue. transaction has entered the delayed transaction queue, but target response has not been received. target response was received, but the posted memory write ordering rule prevents the cycle from completing. delayed transaction queue is full; therefore, transaction cannot be queued. transaction with the same address and command was queued. locked sequence is being propagated across the pci 6150, and the write transaction is not a locked transaction. target bus is locked and the write transaction is a locked transaction. delayed read transactions transaction is in the process of entering the delayed transaction queue. read request was queued, but read data is not yet available. data was read from the target, but the data is not at the head of the read data queue, or a posted write transaction precedes it. delayed transaction queue is full, and the transaction cannot be queued. delayed read request with the same address and bus command was queued. locked sequence is being propagated across the pci 6150, and the read transaction is not a locked transaction. target bus is locked and the read transaction is a locked transaction. posted write transactions posted write data buffer does not contain sufficient space for the address and at least two qwords of write data. locked sequence is being propagated across the pci 6150, and the write transaction is not a locked transaction. when a target retry is returned to a delayed transaction initiator, the initiator must repeat the transaction with the same address and bus command, as well as the data if this is a write transaction, within the time frame specified by the master timeout value; otherwise, the transaction is discarded from the buffers. section 8 pci bus operation transaction termination pci 6150bb data book, version 2.11 8-18 ? 2005 plx technology, inc. all rights reserved. 8.6.4.2 target disconnect the pci 6150 returns a target disconnect to an initiator when the pci 6150: reaches an internal address boundary reaches a 4-kb boundary for a posted memory write cycle cannot accept further write data contains no further read data to deliver 8.6.4.3 target abort the pci 6150 returns a target abort to an initiator when the pci 6150: returns a target abort from the intended target detects a master abort on the target, and the master abort mode bit is set (bcntrl[5]=1; pci:3eh) cannot obtain delayed read data from the target nor deliver delayed write data to the target after 2 24 attempts when returning a target abort to the initiator, the pci 6150 sets the status register signaled target abort bit corresponding to the initiator interface (pcisr[12 or 11]=1; pci:06h). pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 9-1 9?address decoding 9 address decoding this section describes address decoding, including address ranges, memory address decoding, isa mode, and vga addressing support. 9.1 overview the pci 6150 uses three address ranges to control i/o and memory transaction forwarding across the bridge. these address ranges are defined by base and limit address registers in configuration space. 9.2 address ranges the pci 6150 uses the following address ranges to determine which i/o and memory transactions are forwarded from the primary-to-secondary pci bus, and from the secondary-to-primary pci bus: one 32-bit i/o address range one 32-bit memory-mapped i/o (non-prefetchable memory) range one 64-bit prefetchable memory address range transaction addresses falling within these ranges are forwarded downstream from the primary-to-secondary pci bus. transaction addresses falling outside these ranges are forwarded upstream from the secondary- to-primary pci bus. the pci 6150 uses flat address space ( that is , it does not perform address translation). the address space has no gaps; therefore, addresses that are not marked for downstream forwarding are always forwarded upstream. 9.2.1 i/o address decoding the pci 6150 uses the following mechanisms, defined in configuration space, to specify the i/o address space for downstream and upstream forwarding: i/o base and limit address registers (base? pciiobar; pci:1ch and pciiobaru16; pci:30h, limit?pciiolmt; pci:1dh and pciiolmtu16; pci:32h) isa enable bit (bcntrl[2]; pci:3eh) vga enable bit (bcntrl[3]; pci:3eh) vga palette snoop enable bit (pcicr[5]; pci:04h) to enable downstream i/o transaction forwarding, the command register i/o space enable bit must be set (pcicr[0]=1; pci:04h). if the i/o space enable bit is not set, i/o transactions initiated on the primary bus are ignored. to enable upstream i/o transaction forwarding, the command register master enable bit must be set (pcicr[2]=1; pci:04h). if the master enable bit is not set, the pci 6150 ignores i/o and memory transactions initiated on the secondary bus. setting the master enable bit also allows upstream memory transaction forwarding. caution: if any configuration state affecting i/o transaction forwarding is changed by a configuration write operation on the primary bus when there are ongoing i/o transactions on the secondary bus, the pci 6150 response to the secondary bus i/o transactions is unpredictable. configure the i/o base and limit address registers, and isa enable, vga enable, and vga palette snoop enable bits before setting the i/o space enable and master enable bits, and subsequently change these registers only when the primary and secondary pci buses are idle. 9.2.1.1 i/o base and limit address registers the pci 6150 implements one set of i/o base and limit address registers in configuration space that define an i/o address range for downstream forwarding. the pci 6150 supports 32-bit i/o addressing, which allows i/o addresses downstream from the pci 6150 to be mapped anywhere in a 4-gb i/o address space. i/o transactions with addresses that fall inside the i/o base and limit register-defined range are forwarded downstream from the primary-to-secondary pci bus. i/o transactions with addresses that fall outside this range are forwarded upstream from the secondary-to- primary pci bus. the i/o range can be disabled by setting the i/o base address to a value greater than that of the i/o limit address. when the i/o range is disabled, all i/o transactions are forwarded upstream (no i/o transactions are forwarded downstream). the i/o range has a minimum granularity of 4 kb and is aligned on a 4-kb boundary. the maximum i/o range is 4 gb. section 9 address decoding memory address decoding pci 6150bb data book, version 2.11 9-2 ? 2005 plx technology, inc. all rights reserved. the i/o base register consists of an 8-bit field (pciiobar; pci:1ch) and a 16-bit field (pciiobaru16; pci:30h). the upper four bits of the 8-bit field define bits [15:12] of the i/o base address. the lower four read-only bits are hardcoded to 0001b to indicate 32-bit i/o addressing support. bits [11:0] of the base address are assumed to be 0h, which naturally aligns the base address to a 4-kb boundary with a minimum granularity of 4 kb. the 16 bits contained in the i/o base upper 16 bits register (pciiobaru16; pci:30h) define ad[31:16] of the i/o base address. all 16 bits are read/write. after a primary bus or chip reset, the i/o base address value is initialized to 0000_0001h. the i/o limit register consists of an 8-bit field (pciiolmt; pci:1dh) and a 16-bit field (pciiolmtu16; pci:32h). the upper four bits of the 8-bit field define bits [15:12] of the i/o limit address. the lower four read-only bits are hardcoded to 0001b to indicate 32-bit i/o addressing support. bits [11:0] of the limit address are assumed to be fffh, which naturally aligns the limit address to the top of a 4-kb i/o address block. the 16 bits contained in the i/o limit upper 16 bits register (pciiolmtu16; pci:32h) define ad[31:16] of the i/o limit address. all 16 bits are read/write. after a primary bus or chip reset, the i/o limit address value is reset to 0000_ 0fffh. note: the initial states of the i/o base and limit registers (pciiobar; pci:1ch and pciiolmt; pci:1dh, respectively) define an i/o range of 0000_0000h to 0000_0fffh, which is the lower 4 kb of i/o space. write these registers with their appropriate values before setting the command register master or i/o space enable bit (pcicr[2 or 0]=1; pci:04h). 9.3 memory address decoding the pci 6150 has three mechanisms for defining memory address ranges for memory transaction forwarding: memory-mapped i/o base and limit address registers (pcimbar; pci:20h and pcimlmt; pci:22h, respectively) prefetchable memory base and limit address registers (base?pcipmbar; pci:24h and pcipmbaru32; pci:28h, limit?pcipmlmt; pci:26h and pcipmlmtu32; pci:2ch) vga mode (bcntrl[3]=1; pci:3eh) this subsection describes the first two mechanisms. vga mode is described in section 9.5.1. to enable downstream memory transaction forwarding, the command register memory space enable bit must be set (pcicr[1]=1; pci:04h). to enable upstream memory transaction forwarding, the command register master enable bit must be set (pcicr[2]=1; pci:04h). setting the master enable bit also enables upstream i/o transaction forwarding. caution: if any configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus when there are ongoing memory transactions on the secondary bus, response to the secondary bus memory transactions is unpredictable. configure the memory-mapped i/o base and limit address registers, prefetchable memory base and limit address registers, and vga enable bit before setting the memory space enable and master enable bits, and subsequently change these registers only when the primary and secondary pci buses are idle. 9.3.1 memory-mapped i/o base and limit address registers memory-mapped i/o is also referred to as non-prefetchable memory. memory addresses that cannot be automatically prefetched, but can conditionally prefetch based on command type, should be mapped into this space. read transactions to non-prefetchable space may exhibit side effects? may exhibit non-memory-like behavior. the pci 6150 prefetches in this space only if the memory read line or memory read multiple commands are used. transactions using the memory read command are limited to a single data transfer. the memory-mapped i/o base and limit address registers define an address range that the pci 6150 uses to determine when to forward memory commands. the pci 6150 forwards a memory transaction from the primary-to-secondary interface if the transaction address falls within the memory- mapped i/o address range. the pci 6150 ignores memory transactions initiated on the secondary interface that fall into this address range. transactions that fall outside this address range are ignored on the primary interface and forwarded upstream from the secondary interface (provided that the transactions do not fall into the prefetchable memory range, or are not forwarded downstream by the vga mechanism). section 9 memory address decoding address decoding pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 9-3 9?address decoding the memory-mapped i/o address range supports only 32-bit addressing. p-to-p bridge r1.1 does not provide for 64-bit addressing in the memory-mapped i/o space. the memory-mapped i/o address range has a granularity and alignment of 1 mb and a maximum range of 4 gb. the memory-mapped i/o address range is defined by a 16-bit memory-mapped i/o base address register (bar) and a 16-bit memory-mapped i/o limit address register (pcimbar; pci:20h and pcimlmt; pci:22h, respectively). the upper 12 bits of each of these registers correspond to bits [31:20] of the memory address. the lower four bits are hardcoded to 0h. the lower 20 bits of the memory-mapped i/o base address are assumed to be 0h, which results in a natural alignment to a 1-mb boundary. the lower 20 bits of the memory-mapped i/o limit address are assumed to be f_ffffh, which results in an alignment to the top of a 1-mb block. note: the initial state of the memory-mapped i/o base address register (pcimbar; pci:20h) is 0000_0000h. the initial state of the memory-mapped i/o limit address register (pcimlmt; pci:22h) is 000f_ffffh. the initial states of these registers define a memory- mapped i/o range at the lower 1-mb memory block. write these registers with their appropriate values before setting the command register master or memory spac e enable bit (pcicr[2 or 1]=1; pci:04h). to disable the memory-mapped i/o address range, write the memory-mapped i/o base address register with a value greater than that of the memory-mapped i/o limit address register. 9.3.1.1 prefetchable memory base and limit address registers locations accessed in the prefetchable memory address range must have true memory-like behavior and not exhibit side effects when read ( that is , extra reads to a prefetchable memory location must not have side effects). the pci 6150 prefetches for all types of memory read commands in this address space. the pci 6150 prefetchable memory base and limit address registers define an address range that the pci 6150 uses to determine when to forward memory transactions. the pci 6150 forwards a memory transaction from the primary-to-secondary interface, if the transaction address falls within the prefetchable memory address range. the pci 6150 ignores memory transactions initiated on the secondary interface that fall into this address range. the pci 6150 does not respond to transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that the transactions do not fall into the memory-mapped i/o address range, or are not forwarded by the vga mechanism). the pci 6150 prefetchable memory range supports 64-bit addressing and provides additional registers to define the upper 32 bits of the prefetchable memory base and limit addresses. for address comparison, a single address cycle (sac; 32-bit address) prefetchable memory transaction is treated as a 64-bit address transaction, where the upper 32 bits of the address are equal to 0h. this upper 32-bit value of 0h is compared to the prefetchable memory base and limit address upper 32 bits registers. the prefetchable memory base address upper 32 bits register must be 0h to pass sac transactions downstream. the prefetchable memory address range is defined by a 16-bit prefetchable memory base address register and a 16-bit prefetchable memory limit address register (pcipmbar; pci:24h and pcipmlmt; pci:26h, respectively). the upper 12 bits of each of these registers correspond to bits [31:20] of the memory address. the lower four read-only bits are hardcoded to 1h, indicating 64-bit address support. the lower 20 bits of the prefetchable memory base address are assumed to be 0h, which results in a natural alignment to a 1-mb boundary. the lower 20 bits of the prefetchable memory limit address are assumed to be f_ffffh, which results in an alignment to the top of a 1-mb block. the maximum memory address range is 4 gb for 32-bit addressing, and 2 64 bytes for 64-bit addressing. note: write the pcipmbar and pcipmlmt registers with their appropriate values before setti ng the command register memory space enable or master enable bit. to disable the prefetchable memory address range, write the prefetchable memory base address register with a value greater than that of the prefetchable memory limit address register. the entire base register value must be greater than the entire limit register value ( that is , the upper 32 bits must be considered). therefore, to disable the address range, the upper 32 bits registers can both be set to the section 9 address decoding isa mode pci 6150bb data book, version 2.11 9-4 ? 2005 plx technology, inc. all rights reserved. same value, while the lower base register is set to a value greater than that of the lower limit register; otherwise, the upper 32-bit base register must be greater than the upper 32-bit limit register. 9.4 isa mode the pci 6150 supports isa mode by providing the bridge control register isa enable bit in configuration space (bcntrl[2]=1; pci:3eh). isa mode modifies the pci 6150 response inside the i/o address range to support i/o space mapping in the presence of an isa bus in the system. this bit only affects the pci 6150 response when the following conditions are met: transaction falls inside the address range defined by the i/o base and limit address registers, and address also falls inside the first 64 kb of i/o space (address bits [31:16]=0h) when the isa enable bit is set, the pci 6150 does not forward downstream i/o transactions that address the upper 768 bytes of each aligned 1-kb block. only those transactions addressing the lower 256 bytes of an aligned 1-kb block inside the base and limit i/o address range are forwarded downstream. transactions above the 64-kb i/o address boundary are forwarded, as defined by the i/o base and limit register address range. additionally, if the isa enable bit is set, the pci 6150 forwards upstream those i/o transactions that address the upper 768 bytes of each aligned 1-kb block within the first 64 kb of i/o space. the command configuration register master enable bit must also be set (pcicr[2]=1; pci:04h) to enable upstream forwarding. all other i/o transactions initiated on the secondary bus are forwarded upstream if the transactions fall outside the i/o address range. when the isa enable bit is set, devices downstream of the pci 6150 can have i/o space mapped into the first 256 bytes of each 1-kb segment below the 64-kb boundary, or anywhere in i/o space above the 64-kb boundary. 9.5 vga support the pci 6150 provides two modes for vga support: vga mode, supporting vga-compatible addressing vga snoop mode, supporting vga palette forwarding 9.5.1 vga mode when a vga-compatible device exists downstream from the pci 6150, enable vga mode by setting the bridge control register vga enable bit (bcntrl[3]=1; pci:3eh). when operating in vga mode, the pci 6150 forwards downstream those transactions that address the vga frame buffer memory and vga i/o registers, regardless of the i/o base and limit address register values. the pci 6150 ignores transactions initiated on the secondary interface addressing these locations. the vga frame buffer resides in the memory address range?000a_0000h to 000b_ffffh. read transactions to frame buffer memory are treated as non-prefetchable. the pci 6150 requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus. the vga i/o addresses consist of i/o addresses 3b0h to 3bbh and 3c0h to 3dfh. these i/o addresses are aliased every 1 kb throughout the first 64 kb of i/o space [ that is , address bits [15:10] are not decoded and can be any value, while address bits [31:16] must be all zeros (0)]. vga bios addresses starting at c_0000h are not decoded in vga mode. section 9 vga support address decoding pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 9-5 9?address decoding 9.5.2 vga snoop mode the pci 6150 provides vga snoop mode, allowing for vga palette write transactions to be forwarded downstream. this mode is used when a graphics device downstream from the pci 6150 must snoop or respond to vga palette write transactions. to enable the mode, set the command register vga palette snoop enable bit (pcicr[5]=1; pci:04h). the pci 6150 claims vga palette write transactions by asserting devsel# in vga snoop mode. when the vga palette snoop enable bit is set, the pci 6150 forwards downstream transactions with i/o addresses 3c6h, 3c8h, and 3c9h. these addresses are also forwarded as part of the previously described vga compatibility mode. again, address bits [15:10] are not decoded, while address bits [31:16] must be equal to 0h ( that is , these addresses are aliased every 1 kb throughout the first 64 kb of i/o space). note: if bcntrl[3]=1; pci:3eh (vga enable bit), then vga palette accesses are forwarded, regardless of the pcicr[5]; pci:04h value. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 10-1 10?transaction ordering 10 transaction ordering this section describes the ordering rules that control pci transaction forwarding across the pci 6150. to maintain data coherency and consistency, the pci 6150 complies with pci r2.3 ordering rules . for a detailed discussion of transaction ordering, refer to pci r2.3, appendix e. 10.1 transactions governed by ordering rules ordering relationships are established for the following transaction classes that cross the pci 6150: posted write transactions (comprised of memory write, and memory write and invalidate, transactions) ?completed at the source before completing at the destination ( that is , data is written into intermediate data buffers before reaching the target). delayed write request transactions (comprised of i/o write and configuration write transactions) ?terminated by target retry on the initiator bus and queued in the delayed transaction queue. a delayed write transaction must complete on the target bus before completing on the initiator bus. delayed write completion transactions (comprised of i/o write and configuration write transactions) ?completed on the target bus, with the target response queued in the buffers. a delayed write completion transaction proceeds in the direction opposite to that of the original delayed write request ( that is , the transaction proceeds from target-to-initiator bus). delayed read request transactions (comprised of all memory read, i/o read, and configuration read transactions) ?terminated by target retry on the initiator bus and queued in the delayed transaction queue. delayed read completion transactions (comprised of all memory read, i/o read, and configuration read transactions) ?completed on the target bus, and the read data was queued in the read data buffers. a delayed read completion transaction proceeds in the direction opposite that of the original delayed read request ( that is , the transaction proceeds from target-to-initiator bus). the pci 6150 does not combine, merge, nor collapse write transactions: combine separate write transactions into a single write transaction ?this optimization is best implemented in the originating master. merge bytes on separate masked write transactions to the same dword address ? this optimization is also best implemented in the originating master. collapse sequential write transactions to the same address into a single write transaction ? pci r2.3 does not allow collapsing of transactions. 10.2 general ordering guidelines pci-independent transactions on the primary and secondary buses have a relationship only when those transactions cross the pci 6150. the following general ordering guidelines govern transactions crossing the pci 6150: ordering relationship of a transaction, with respect to other transactions, is determined when the transaction completes ( that is , when a transaction ends with a termination other than target retry). requests terminated with a target retry can be accepted and completed in any order with respect to other transactions terminated with a target retry. if the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one completes. if more than one delayed transaction is initiated, the initiator should repeat all the delayed transaction requests, using a fairness algorithm. repeating a delayed transaction cannot be contingent upon completion of another delayed transaction; otherwise, deadlock may occur. write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. the pci 6150 can simultaneously accept posted write transactions on both interfaces, as well as simultaneously initiate posted write transactions on both interfaces. section 10 transaction ordering ordering rules pci 6150bb data book, version 2.11 10-2 ? 2005 plx technology, inc. all rights reserved. acceptance of a posted memory write transaction as a target can never be contingent on the completion of an unlocked, unposted transaction as a master. this is true of the pci 6150 and must also be true of other bus agents; otherwise, deadlock may occur. pci 6150 accepts posted write transactions, regardless of the state of completion of delayed transactions being forwarded across the pci 6150. 10.3 ordering rules the following ordering rules describe the transaction relationships. each ordering rule is followed by an explanation, and the ordering rules are referred to by number in table 10-1. these ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing the pci 6150 in the same direction. note that delayed completion transactions cross the pci 6150 in the direction opposite that of the corresponding delayed requests. 1. posted write ?posted write transactions must complete on the target bus in the order in which the transactions were received on the initiator bus. the subsequent posted write transaction could be setting a flag that covers the data in the first posted write transaction. if the second transaction were to complete before the first transaction, devices checking that flag could subsequently be using stale data. 2. delayed write request ?delayed write requests cannot pass previously queued posted write data. as in the case of posted memory write transactions, the delayed write transaction might be setting a flag regarding data in the posted write transaction. if the delayed write request were to complete before the earlier posted write transaction, devices checking the flag could subsequently be using stale data. 3. delayed read request ?delayed read requests traveling in the same direction as previously queued posted write transactions must push the posted write data ahead of it. the posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. the read transaction might be in the same location as the write data; therefore, if the read transaction were to pass the write transaction, the read would return stale data. 4. delayed write completion ?posted write transactions must be provided opportunities to pass delayed read and write requests and completions. otherwise, deadlock may occur when bridges that support delayed transactions are used in the same system with bridges that do not support delayed transactions. a fairness algorithm is used to arbitrate between the posted write and delayed transaction queues. the pci 6150 can return delayed read transactions in a different order than requested if the drt out-of-order enable bit is set to 1 (mscopt[2]=1; pci:46h). requested cycles can execute out of order across the bridge, if all other ordering rules are satisfied. therefore, if the pci 6150 starts a delayed transaction that is retried by the target, the pci 6150 can execute another transaction in the delayed transaction request queue. also, if there are delayed write and read requests in the queue, and the read data fifos are full, the pci 6150 may execute the delayed write request before the delayed read request. 5. delayed read completion ?delayed read completions must ?pull? ahead of previously queued posted write data traveling in the same direction. in this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of the bridge as the target of the write transaction. the posted write transaction must complete on the target before read data is returned to the initiator. the read transaction could be to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete.the pci 6150 can generate cycles across the bridge in the same order requested if the miscellaneous options register drt out-of-order enable bit is set (mscopt[2]=1; pci:46h). by default, requested cycles can execute out of order across the bridge if all other ordering rules are satisfied. therefore, if the pci 6150 begins a delayed transaction that is retried by the target, the pci 6150 can execute another transaction in the delayed transaction request queue. additionally, if there is both delayed write and delayed read requests in the queue, and the read data fifo is full, the pci 6150 may execute the delayed write request before the delayed read request. section 10 data synchronization transaction ordering pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 10-3 10?transaction ordering on cycle completion, the pci 6150 may complete cycles in a different order than that requested by the initiator. 10.4 data synchronization data synchronization refers to the relationship between interrupt signaling and data delivery. pci r2.3 provides the following alternative methods for synchronizing data and interrupts: device signaling the interrupt performs a read of the data just written (software) device driver performs a read operation to any register in the interrupting device before accessing data written by the device (software) system hardware guarantees that write buffers are flushed before interrupts are forwarded the pci 6150 does not have a hardware mechanism to guarantee data synchronization for posted write transactions. therefore, all posted write transactions must be followed by a read operation, from the pci 6150 to the location recently written (or some other location along the same path), or from the device driver to a pci 6150 register. table 10-1. transaction ordering summary pass posted write delayed write request delayed read request delayed write completion delayed read completion posted write n 1 y 4 y 4 y 4 y 4 delayed write request n 5 yyyy delayed read request n 3 yyyy delayed write completion yyyyy delayed read completion n 2 yyyy legend : superscript number = refers to the five applicable ordering rules listed in section 10.3. many entries are not governed by these ordering rules; therefore, the implementation c an choose whether the transactions pass each other. y = transactions may be completed out of order or ?pass? each other. n = row transaction must not pass the column transaction. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 11-1 11?error handling 11 error handling this section provides detailed information regarding pci 6150 error management. it also describes error status reporting and error operation disabling. 11.1 overview the pci 6150 checks, forwards, and generates parity on the primary and secondary interfaces. to maintain transparency, the pci 6150 forwards the existing parity condition from one bus to the other, along with address and data, or regenerates the data parity on the other bus (mscopt[3]=1; pci:46h). to support error reporting on the pci bus, the pci 6150 implements the following: p_perr#, p_serr#, s_perr#, and s_serr# signals primary and secondary status registers (pcisr; pci:06h and pcissr; pci:1eh, respectively) device-specific p_serr# event disable and status registers (pserred; pci:64h and pserrsr; pci:6ah, respectively) 11.2 address parity errors the pci 6150 checks address parity for all bus transactions, and address and bus commands. when the pci 6150 detects an address parity error on the primary interface, the following occurs: 1. if the command register parity error response enable bit is set (pcicr[6]=1; pci:04h), the pci 6150 does not claim the transaction with p_devsel#. this may allow the transaction to terminate in a master abort. if the parity error response enable bit is not set, the pci 6150 proceeds as usual and accepts the transaction if the transaction is directed to, or across, the pci 6150. 2. pci 6150 sets the status register parity error detected bit (pcisr[15]=1; pci:06h). 3. pci 6150 asserts p_serr# and sets the status register signaled system error bit (pcisr[14]=1), if the command register p_serr# enable and parity error response enable bits are set (pcicr[8, 6]=11b; pci:04h). when the pci 6150 detects an address parity error on the secondary interface, the following occurs: 1. if the bridge control register parity error response enable bit is set (bcntrl[0]=1; pci:3eh), the pci 6150 does not claim the transaction with s_devsel#. this may allow the transaction to terminate in a master abort. if the parity error response enable bit is not set, the pci 6150 proceeds as usual and accepts the transaction if the transaction is directed to, or across, the pci 6150. 2. pci 6150 sets the secondary status register parity error detected bit (pcissr[15]=1; pci:1eh), regardless of the parity error response enable bit state (pcicr[6]=x). 3. pci 6150 asserts s_serr# and sets the status register signaled system error bit (pcissr[14]=1). 11.3 data parity errors when forwarding transactions, the pci 6150 attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to manage the error condition. the following subsections describe, for each transaction, the sequence that occurs when a parity error is detected and the way in which the parity condition is forwarded across the bridge. 11.3.1 configuration write transactions to configuration space when the pci 6150 detects a data parity error during a type 0 configuration write transaction to configuration space, the following occurs: 1. if the command register parity error response enable bit is set (pcicr[6]=1; pci:04h), the pci 6150 asserts p_perr#. if the parity error response enable bit is not set, the pci 6150 does not assert p_perr#. in either case, the configuration register is written. 2. pci 6150 sets the status register parity error detected bit (pcisr[15]=1; pci:06h), regardless of the parity error response enable bit state (pcicr[6]=x). section 11 error handling data parity errors pci 6150bb data book, version 2.11 11-2 ? 2005 plx technology, inc. all rights reserved. 11.3.2 read transactions when the pci 6150 detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts p_perr# or s_perr#. for downstream transactions, when the pci 6150 detects a read data parity error on the secondary bus, the pci 6150: 1. asserts s_perr# two cycles following the data transfer, if the secondary interface bridge control register parity error response enable bit is set (bcntrl[0]=1; pci:3eh). 2. sets the secondary status register parity error detected bit (pcissr[15]=1; pci:1eh), regardless of the parity error response enable bit state (pcicr[6]=x). 3. sets the secondary status register data parity error detected bit (pcissr[8]=1), if bcntrl[0]=1. 4. returns the bad parity with the data to the initiator on the primary bus. if the data with the bad parity is prefetched and not read by the initiator on the primary bus, the data is discarded and data with bad parity is not returned to the initiator. 5. completes the transaction as usual. for upstream transactions, when the pci 6150 detects a read data parity error on the primary bus, the pci 6150: 1. asserts p_perr# two cycles following the data transfer, if the primary interface command register parity error response enable bit is set (pcicr[6]=1). 2. sets the primary status register parity error detected bit (pcisr[15]=1). 3. sets the primary status register data parity error detected bit (pcisr[8]=1), if pcicr[6]=1. 4. returns the bad parity with the data to the initiator on the secondary bus. if the data with the bad parity is prefetched and not read by the initiator on the secondary bus, the data is discarded and data with bad parity is not returned to the initiator. 5. completes the transaction as usual. the pci 6150 returns to the initiator the data and parity received from the target. when the initiator detects a parity error on this read data and is enabled to report the error, the initiator asserts its perr# signal (which is then connected to the pci 6150 p_perr# or s_perr# signal, depending on the initiator bus) two cycles after the data transfer. it is assumed that the initiator is responsible for handling parity error conditions; therefore, when the pci 6150 detects the initiator?s perr# assertion while returning read data to the initiator, the pci 6150 takes no further action and completes the transaction as usual. 11.3.3 posted write transactions during downstream posted write transactions, when the pci 6150 is responding as a target and detects a data parity error on the initiator (primary) bus, it: 1. asserts p_perr# two cycles after the data transfer, if the primary interface command register parity error response enable bit is set (pcicr[6]=1). 2. sets the primary interface status register parity error detected bit (pcisr[15]=1). 3. captures and forwards the bad parity condition to the secondary bus. 4. completes the transaction as usual. similarly, during upstream posted write transactions, when the pci 6150 is responding as a target and detects a data parity error on the initiator (secondary) bus, it: 1. asserts s_perr# two cycles after the data transfer, if the secondary interface bridge control register parity error response enable bit is set (bcntrl[0]=1). 2. sets the secondary interface status register parity error detected bit (pcissr[15]=1), regardless of the parity error response enable bit state (pcicr[6]=x). 3. captures and forwards the bad parity condition to the primary bus. 4. completes the transaction as usual. section 11 data parity errors error handling pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 11-3 11?error handling during downstream write transactions, when a data parity error is reported on the target (secondary) bus by the target?s assertion of s_perr#, the pci 6150: 1. sets the secondary status register data parity error detected bit (pcissr[8]=1), if the secondary interface bridge control register parity error response enable bit is set (bcntrl[0]=1). 2. asserts p_serr# and sets the status register signaled system error bit (pcisr[14]=1), if the following conditions are met: primary interface command register p_serr# enable and parity error response enable bits are set (pcicr[8, 6]=11b, respectively), and device-specific p_serr# disable bit for posted write parity errors is not set (pserred[1]=0; pci:64h), and secondary interface bridge control register parity error response enable bit is set (bcntrl[0]=1), and pci 6150 did not detect the parity error on the initiator (primary) bus ( that is , the parity error was not forwarded from the primary bus) during upstream write transactions, when a data parity error is reported on the target (primary) bus by the target?s assertion of p_perr#, the pci 6150: 1. sets the status register data parity error detected bit (pcisr[8]=1), if the primary interface command register parity error response enable bit is set (pcicr[6]=1). 2. asserts p_serr# and sets the status register signaled system error bit (pcisr[14]=1), if the following conditions are met: primary interface command register p_serr# enable and parity error response enable bits are set (pcicr[8, 6]=11b, respectively), and secondary interface bridge control register parity error response enable bit is set (bcntrl[0]=1), and pci 6150 did not detect the parity error on the initiator (secondary) bus ( that is , the parity error was not forwarded from the secondary bus) p_serr# assertion signals the parity error condition when the initiator is not sent information about an error having occurred. because the data is delivered with no errors, there is no other way to signal this information to the initiator. if a parity error is forwarded from the initiator bus to the target bus, p_serr# is not asserted. 11.3.4 delayed write transactions when the pci 6150 detects a data parity error during a delayed write transaction, it conditionally asserts perr#. the pci 6150 passes or regenerates data parity to the target bus (mscopt[3]=1; pci:46h). a parity error can occur: during the original delayed write request transaction when the initiator repeats the delayed write request transaction when the pci 6150 completes the delayed write transaction to the target when a delayed write transaction is queued, the address, command, address and data parity, data, and byte enable bits are captured and a target retry is returned to the initiator. when the pci 6150 detects a parity error on the write data for the initial delayed write request transaction, the following occurs: 1. if the parity error response enable bit corresponding to the initiator bus is set (primary? pcicr[6]=1, secondary?bcntrl[0]=1), the pci 6150 asserts p_perr# or s_perr# two clocks after the data. the pci 6150 always accepts the cycle, and can optionally pass the incorrect parity to the other bus, or regenerate data parity on the other bus (mscopt[3]=1; pci:46h). 2. pci 6150 sets the status register parity error detected bit corresponding to the initiator bus (primary?pcisr[15]=1, secondary? pcissr[15]=1), regardless of the parity error response enable bit state (pcicr[6]=x). following the initiating transaction (the first pci 6150 retry), the subsequent data parity error of a similar transaction on the initiating bus is detected as usual; however, the data parity error no longer affects fifo operation. the cycles are considered similar if they have the same address, command, byte enables and write data. the parity bit is not part of this ?similar? detection operation. therefore, if a data parity error occurs only in the parity bit (same data as before), the cycle operates as usual. conversely, if a data parity error occurs in the data segment (different data from the initiating write data), the pci 6150 treats the error as a new delayed write transaction. section 11 error handling data parity error reporting summary pci 6150bb data book, version 2.11 11-4 ? 2005 plx technology, inc. all rights reserved. 11.4 data parity error reporting summary in the previous subsections, the pci 6150 responses to data parity errors are presented according to transaction type in progress. this subsection organizes the pci 6150 responses to data parity errors according to the status bits set by the pci 6150 and the signals asserted. table 11-1 delineates the primary interface status register parity error detected bit status. this bit is set when the pci 6150 detects a parity error on the primary interface. table 11-2 delineates the secondary interface status register parity error detected bit status. this bit is set when the pci 6150 detects a parity error on the secondary interface. table 11-3 delineates the primary interface status register data parity error detected bit status. this bit is set under the following conditions: pci 6150 must be a master on the primary bus, and primary interface command register parity error response enable bit must be set (pcicr[6]=1), and p_perr# is detected asserted, or a parity error is detected on the primary bus table 11-4 delineates the secondary interface status register data parity error detected bit status. this bit is set under the following conditions: pci 6150 must be a master on the secondary bus, and secondary interface bridge control register parity error response enable bit must be set (bcntrl[0]=1), and s_perr# is detected asserted, or a parity error is detected on the secondary bus table 11-5 delineates p_perr# assertion. this signal is set under the following conditions: pci 6150 is either the target of a write transaction or the initiator of a read transaction on the primary bus, and primary interface command register parity error response enable bit must be set (pcicr[6]=1), and pci 6150 detects a data parity error on the primary bus, or detects s_perr# asserted during the completion phase of a downstream delayed write transaction on the target (secondary) bus table 11-6 delineates s_perr# assertion. this signal is set under the following conditions: pci 6150 is either the target of a write transaction or the initiator of a read transaction on the secondary bus, and secondary interface bridge control register parity error response enable bit must be set (bcntrl[0]=1), and pci 6150 detects a data parity error on the secondary bus, or detects p_perr# asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus table 11-7 delineates p_serr# or s_serr# assertion. this signal is set under the following conditions: command register p_serr# enable and parity error response enable bits must be set (pcicr[8, 6]=11b, respectively), and bridge control register parity error response enable bit must be set (bcntrl[0]=1), and pci 6150 detects s_perr# asserted on a downstream posted write transaction, or p_perr# asserted on an upstream posted write transaction, and pci 6150 did not detect the parity error as a target of the posted write transaction section 11 data parity error reporting summary error handling pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 11-5 11?error handling note: x = don?t care. table 11-1. primary interface pa rity error detected bit status primary parity error detected bit (pcisr[15]) transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 0 read downstream primary x x 0 secondary x x 1 upstream primary x x 0 secondary x x 1 posted write downstream primary x x 0 secondary x x 0 upstream primary x x 0 secondary x x 1 delayed write downstream primary x x 0 secondary x x 0 upstream primary x x 0 secondary x x section 11 error handling data parity error reporting summary pci 6150bb data book, version 2.11 11-6 ? 2005 plx technology, inc. all rights reserved. note: x = don?t care. table 11-2. secondary interface parity error detected bit status secondary parity error detected bit (pcissr[15]) transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 0 read downstream primary x x 1 secondary x x 0 upstream primary x x 0 secondary x x 0 posted write downstream primary x x 0 secondary x x 0 upstream primary x x 1 secondary x x 0 delayed write downstream primary x x 0 secondary x x 0 upstream primary x x 1 secondary x x section 11 data parity error reporting summary error handling pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 11-7 11?error handling note: x = don?t care. table 11-3. primary interface data parity error detected bit status primary data parity error detected bit (pcisr[8]) transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 0 read downstream primary x x 0 secondary x x 1 upstream primary 1 x 0 secondary x x 0 posted write downstream primary x x 0 secondary x x 1 upstream primary 1 x 0 secondary x x 0 delayed write downstream primary x x 0 secondary x x 1 upstream primary 1 x 0 secondary x x section 11 error handling data parity error reporting summary pci 6150bb data book, version 2.11 11-8 ? 2005 plx technology, inc. all rights reserved. note: x = don?t care. table 11-4. secondary interface data parity error detected bit status secondary data parity error detected bit (pcissr[8]) transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 0 read downstream primary x x 1 secondary x 1 0 upstream primary x x 0 secondary x x 0 posted write downstream primary x x 1 secondary x 1 0 upstream primary x x 0 secondary x x 0 delayed write downstream primary x x 1 secondary x 1 0 upstream primary x x 0 secondary x x section 11 data parity error reporting summary error handling pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 11-9 11?error handling notes: x = don?t care. * parity error detected on the target (secondary) bus, but not on the initiator (primary) bus. table 11-5. p_perr# assertion p_perr# transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 1 (de-asserted) read downstream primary x x 1 secondary x x 0 (asserted) upstream primary 1 x 1 secondary x x 0 posted write downstream primary 1 x 1 secondary x x 1 upstream primary x x 1 secondary x x 0 delayed write downstream primary 1 x 0* secondary 1 1 1 upstream primary x x 1 secondary x x section 11 error handling data parity error reporting summary pci 6150bb data book, version 2.11 11-10 ? 2005 plx technology, inc. all rights reserved. notes: x = don?t care. * parity error detected on the target (secondary) bus, but not on the initiator (primary) bus. table 11-6. s_perr# assertion s_perr# transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 1 (de-asserted) read downstream primary x x 0 (asserted) secondary x 1 1 upstream primary x x 1 secondary x x 1 posted write downstream primary x x 1 secondary x x 1 upstream primary x x 0 secondary x 1 1 delayed write downstream primary x x 1 secondary x x 0* upstream primary 1 1 0 secondary x 1 section 11 data parity error reporting summary error handling pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 11-11 11?error handling notes: x = don?t care. * parity error detected on the target (secondary) bus, but not on the initiator (primary) bus. ** parity error detected on the target (primary) bus, but not on the initiator (secondary) bus table 11-7. p _serr# or s_serr# for data parity error assertion p_serr# or s_serr# transaction type direction bus on which error detected primary parity error response enable bit (pcicr[6]) secondary parity error response enable bit (bcntrl[0]) 1 (de-asserted) read downstream primary x x 1 secondary x x 1 upstream primary x x 1 secondary x x 1 posted write downstream primary x x 0* (asserted) secondary 1 1 0** upstream primary 1 1 1 secondary x x 1 delayed write downstream primary x x 1 secondary x x 1 upstream primary x x 1 secondary x x section 11 error handling system error (p_serr#) reporting pci 6150bb data book, version 2.11 11-12 ? 2005 plx technology, inc. all rights reserved. 11.5 system error (p_serr#) reporting the pci 6150 uses the p_serr# signal to conditionally report a number of system error conditions in addition to the special case parity error conditions. in this data book, when p_serr# assertion is discussed, the following conditions are assumed: for the pci 6150 to assert p_serr#, the command register p_serr# enable bit must be set (pcicr[8]=1) when the pci 6150 asserts p_serr#, the pci 6150 must also set the status register signaled system error bit (pcisr[14]=1) in compliance with p-to-p bridge r1.1 , the pci 6150 asserts p_serr# when it detects s_serr# input asserted and the bridge control register s_serr# enable bit is set (bcntrl[1]=1). in addition, the pci 6150 also sets the secondary status register signaled system error bit (pcissr(14]=1). note: s_serr# is an i/o pin. the pci 6150 also conditionally asserts p_serr# for the following conditions: master abort detected during posted write transaction (on the secondary bus) target abort detected during posted write transaction (on the secondary bus) posted write data discarded after 2 24 delivery attempts (2 24 target retries received) s_perr# reported on the target bus during a posted write transaction (refer to section 11.4) delayed write data discarded after 2 24 delivery attempts (2 24 target retries received) delayed read data cannot be transferred from the target after 2 24 attempts (2 24 target retries received) master timeout on delayed transaction the device-specific p_serr# status register reports the reason for p_serr# assertion. most of these events have additional device-specific disable bits in the p_serr# event disable register that can mask p_serr# assertion for specific events. the master timeout condition has s_serr# and p_serr# enable bits for that event in the bridge control register (bcntrl[12:11], respectively), and therefore does not have a device-specific disable bit. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 12-1 12?exclusive access 12 exclusive access this section describes p_lock# and s_lock# signal use to implement exclusive access to a target for transactions crossing the pci 6150, including concurrent locks, and acquiring and ending exclusive access. 12.1 concurrent locks the primary and secondary bus lock mechanisms concurrently operate, except when a locked transaction is crossing the pci 6150. a primary master can lock a primary target without affecting the lock status on the secondary bus, and vice versa. this means that a primary master can lock a primary target concurrent with a secondary master locking a secondary target. 12.2 acquiring exclusive access across pci 6150 for a pci bus, before acquiring access to the p_lock# and/or s_lock# signal and starting a series of locked transactions, the initiator must first verify whether the following conditions are met: pci bus is idle, and p_lock# and/or s_lock# is de-asserted the initiator leaves p_lock# and/or s_lock# de-asserted during the address phase and asserts p_lock# and/or s_lock# one clock cycle later. target lock is achieved after the target completes a data transfer. locked transactions can cross the pci 6150 in the downstream and upstream directions, from the primary-to-secondary bus and vice versa. when the target resides on another pci bus, the master must acquire not only the lock on its own pci bus, but also the lock on every bus between its bus and the target bus. when the pci 6150 detects an initial locked transaction on the primary bus that is intended for a target on the secondary bus, the pci 6150 samples the address, transaction type, byte enable, and parity bits, and the s_lock# signal. because a target retry is signaled to the initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is not yet established. the first locked transaction must be a read transaction. subsequent locked transactions can be write or read transactions. posted memory write transactions that are part of the locked-transaction sequence are nevertheless posted. memory read transactions that are part of the locked-transaction sequence are not prefetched. when the locked delayed read request is queued, the pci 6150 does not queue further transactions until the locked sequence is complete. the pci 6150 signals a target retry to all transactions initiated subsequent to the locked read transaction that are intended for targets on the opposite side of the pci 6150. the pci 6150 allows transactions queued before the locked transaction to complete before initiating the locked transaction. when the locked delayed read request moves to the head of the delayed transaction queue, the pci 6150 initiates the request as a locked read transaction by de-asserting s_lock# on the target bus during the first address phase, then re-asserting s_lock# one cycle later. if s_lock# was previously asserted (used by another initiator), the pci 6150 waits to request access to the secondary bus until s_lock# is sampled de-asserted when the target bus is idle. note that the existing lock on the target bus did not cross the pci 6150; otherwise, the pending queued locked transaction would not have queued. when the pci 6150 is able to complete a data transfer with the locked read transaction, the lock is established on the secondary bus. when the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, byte enable, and parity bits, the pci 6150 transfers the read data back to the initiator, and the lock is also established on the primary bus. for the pci 6150 to recognize and respond to the initiator, the initiator?s subsequent read transaction attempts must use the locked-transaction sequence (de-assert p_lock# during the address phase, then re-assert p_lock# one cycle later). if the p_lock# sequence is not used in subsequent attempts, a master timeout condition may result. when a master timeout condition occurs, p_serr# is conditionally section 12 exclusive access ending exclusive access pci 6150bb data book, version 2.11 12-2 ? 2005 plx technology, inc. all rights reserved. asserted, the read data and queued read transaction are discarded, and s_lock# is de-asserted on the target bus. after the intended target is locked, subsequent locked transactions initiated on the initiator bus that are forwarded by the pci 6150 are driven as locked transactions on the target bus. when the pci 6150 receives a master or target abort in response to the delayed locked read transaction, this status is passed back to the initiator, and no locks are established on the initiator or target bus. the pci 6150 resumes unlocked transaction forwarding in both directions. 12.3 ending exclusive access after the lock is acquired on the initiator and target buses, the pci 6150 must maintain the lock on the target bus for subsequent locked transactions until the initiator relinquishes the lock. the only time a target retry causes the lock to be relinquished is on the first transaction of a locked sequence. on subsequent transactions in the sequence, the target retry has no effect on the p_lock# and/or s_lock# signal status. an established target lock is maintained until the initiator relinquishes the lock. the pci 6150 does not recognize whether the current transaction is the last in a sequence of locked transactions until the initiator de-asserts p_lock# and/or s_lock# at the end of the transaction. when the last locked transaction is a delayed transaction, the pci 6150 previously completed the transaction on the secondary bus. in this case, when the pci 6150 detects that the initiator has relinquished the p_lock# and/or s_lock# signal by sampling the signal de-asserted while p_frame# or s_frame# is de-asserted, the pci 6150 de-asserts p_lock# and/or s_lock# on the target bus when possible. because of this behavior, p_lock# and/or s_lock# may not be de-asserted until several cycles after the last locked transaction completes on the target bus. after de-asserting p_lock# and/or s_lock# to indicate the end of a sequence of locked transactions, the pci 6150 resumes unlocked transaction forwarding. when the last locked transaction is a posted write, the pci 6150 de-asserts p_lock# and/or s_lock# on the target bus at the end of the transaction because the lock was relinquished at the end of the write transaction on the initiator bus. when the pci 6150 receives a master or target abort in response to a locked delayed transaction, the pci 6150 returns a master or target abort when the initiator repeats the locked transaction. the initiator must then de-assert p_lock# and/or s_lock# at the end of the transaction. the pci 6150 sets the appropriate status bits, flagging the abnormal target termination condition, and normal forwarding of unlocked posted and delayed transactions resumes. when the pci 6150 receives a master or target abort in response to a locked posted write transaction, the pci 6150 cannot communicate that status to the initiator. the pci 6150 asserts p_serr# on the initiator bus when a master or target abort is received during a locked posted write transaction, if the command register p_serr# enable bit is set (pcicr[8]=1; pci:04h). p_serr# is asserted for the master abort condition if the bridge control register master abort mode bit is set (bcntrl[5]=1; pci:3eh). note: the pci 6150 has an option to ignore the lock protocol, by clearing the secondary and/or primary lock enable bits (mscopt[14:13]=00b; pci:46h, respectively). pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 13-1 13?pci bus arbitration 13 pci bus arbitration this section describes primary and secondary bus arbitration and bus parking. 13.1 overview the pci 6150 must arbitrate for use of the secondary bus when forwarding downstream transactions, and for the primary bus when forwarding upstream transactions. the primary bus arbiter is external to the pci 6150 (typically located on the motherboard). for the secondary pci bus, the pci 6150 has a built-in internal arbiter. the internal arbiter can be disabled, allowing use of an external arbiter for secondary bus arbitration. 13.2 primary pci bus arbitration the pci 6150 uses one request output pin and one grant input pin (p_req# and p_gnt#, respectively) for primary pci bus arbitration. the pci 6150 asserts p_req# when forwarding transactions upstream ( that is , when operating as an initiator on the primary pci bus). when there are one or more pending transactions in the upstream direction queues? posted write data or delayed transaction requests? the pci 6150 maintains p_req# assertion. however, if a target retry, disconnect, or abort is received in response to a pci 6150-initiated transaction on the primary pci bus, the pci 6150 de-asserts p_req# for two pci clock cycles. for all cycles passing through the bridge, p_req# is not asserted until the complete transaction request is queued. when p_gnt# is asserted low by the primary bus arbiter after the pci 6150 asserts p_req#, the pci 6150 initiates a transaction on the primary bus on behalf of the secondary master. if the primary bus external arbiter asserts the pci 6150 p_gnt# signal when p_req# is not asserted, the pci 6150 parks p_ad[31:0], p_cbe[3:0]#, and p_par by driving these signals to valid logic levels. if the primary bus is parked on the pci 6150 and the pci 6150 has a transaction to initiate on the primary bus, the pci 6150 initiates the transaction if p_gnt# remained asserted during the cycle prior to the start of the transfer. 13.3 secondary pci bus arbitration the pci 6150 implements a secondary pci bus internal arbiter, which supports up to nine external bus masters in addition to the pci 6150. if required, the internal arbiter can be disabled, allowing use of an external arbiter for secondary bus arbitration. 13.3.1 secondary bus arbitration using internal arbiter to use the internal arbiter, the secondary bus internal arbiter enable pin, s_cfn#, must be tied low. the pci 6150 has nine secondary bus request input and grant output pins (s_req[8:0]# and s_gnt[8:0]#, respectively) to support external secondary bus masters. if s_cfn# is high, s_req0# and s_gnt0# are reconfigured as output and input, respectively, and s_gnt[8:1]# are driven high. note: s_req0# and s_gnt0# are i/o pins. the pci 6150 uses a two-level arbitration scheme, whereby arbitration is divided into two groups?low- and high-priority. the low-priority group represents a single entry in the high-priority group. therefore, if the high-priority group consists of n masters, the highest priority is assigned to the low-priority group at least once every n +1 transactions. priority changes evenly among the low-priority group. therefore, assuming all masters request the bus, members of the high-priority group are serviced n transactions out of n +1, while one member of the low-priority group is serviced once every n +1 transactions. each master can be assigned to a low- or high-priority group, through the arbiter control register (acntrl; pci:42h). each group can be programmed to use a rotating- or fixed-priority scheme, through the internal arbiter control register group fixed arbitration bits (iacntrl[2, 0]; pci:50h). section 13 pci bus arbitration secondary pci bus arbitration pci 6150bb data book, version 2.11 13-2 ? 2005 plx technology, inc. all rights reserved. 13.3.2 rotating-priority scheme the secondary arbiter supports a programmable two-level rotating algorithm that enables the nine request/grant pairs to control up to nine external bus masters. in addition, there is a request/grant pair internal to the pci 6150, which allows the device to request and be granted access to the secondary bus. figure 13-1 is an example of the internal arbiter wherein four masters, including the pci 6150, are in the high-priority group, and five masters are in the low-priority group. using this example, if all requests are always asserted, the highest priority rotates among the masters in the following way (the pci 6150 is denoted as b; high-priority members are provided in italic type, and low-priority members in boldface type): b, m0, m1, m2, m3 , b, m0, m1, m2, m4 , b, m0, m1, m2, m5 , and so forth if all masters are assigned to one group, the algorithm defaults to a rotating-priority scheme among all masters. after reset, all external masters are assigned to the low-priority group, and the pci 6150 to the high-priority group. therefore, by default, the pci 6150 receives highest priority on the secondary bus every other transaction and priority rotates evenly among the other masters. figure 13-1. secondary bus arbiter example note: in figure 13-1, ?lpg? denotes ?low-priority group.? priorities are re-evaluated upon s_frame# assertion ( that is , at the start of each new transaction on the secondary pci bus). from this point, until the next transaction starts, the arbiter asserts the grant signal corresponding to the highest priority request asserted. if a grant signal for a particular request is asserted, and a higher priority request subsequently asserts, the arbiter de-asserts the asserted grant signal and asserts the grant signal corresponding to the new higher priority request on the next pci clock cycle. when priorities are re-evaluated, the highest priority is assigned to the next highest priority master, relative to the master that initiated the previous transaction. the master that initiated the last transaction now has the lowest priority within its group. priority is also re-evaluated if the requesting agent de-asserts its request without generating cycles while the request was granted. if the pci 6150 detects that an initiator has failed to assert s_frame# after 16 cycles of grant signal assertion and a secondary bus idle condition, the arbiter re-evaluates grant assignment. if another initiator asserts req# to request the bus, the pci 6150 switches the grant to the new initiator; otherwise, the same grant is asserted to the same initiator, even if the pci 6150 does not assert s_frame# within 16 cycles. 13.3.3 fixed-priority scheme the pci 6150 also supports a fixed-priority scheme within the low- and high-priority groups. in this case, the internal arbiter control register controls whether the low- or high-priority group uses the fixed- or rotating-priority scheme (iacntrl[2, 0]; pci:50h). if using a fixed-priority scheme, a master within the group is assigned the highest priority within its group, and an option is set to control the priority of other masters relative to the highest priority master. this is controlled through the internal arbiter control register highest priority master and group arbitration order bits (iacntrl [11:4, 3, 1]; pci:50h). m1 m2 lpg m0 b m3 m4 m5 m7 m6 section 13 secondary pci bus arbitration pci bus arbitration pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 13-3 13?pci bus arbitration using the example provided in figure 13-1, but with the groups at fixed-priority, suppose that: master 7 (m7) has the highest priority of the low-priority group (iacntrl[7:4]=0111b) pci 6150 (b) has the highest priority of the high-priority group (iacntrl[11:8]=1000b) priority decreases in ascending order of masters for both groups (iacntrl[3, 1]=00b) the order of priority with the highest first is as follows: b, m0, m1, m2, m7 , m3 , m4 , m5 , m6 if iacntrl[3, 1]=11b, priority increases with ascending order of bus master and the order becomes: b , m2 , m1 , m0 , m7 , m6 , m5 , m4 , m3 take care when using fixed arbitration in the low-priority group. as previously noted, the low-priority group receives the grant only when there are no high-priority group requests. when the arbiter switches to the low-priority group, the highest priority master requesting the bus within that group receives the grant. if there are several requests issued by the high-priority group members and the high-priority master in the low-priority group, then lower priority devices in the low-priority group may have to wait before receiving the grant. to prevent bus contention, if the secondary pci bus is idle, the arbiter waits at least one clock cycle between the s_gnt x # de-assertion and assertion of the next s_req x #. if the secondary pci bus is busy ( that is , s_frame# or s_irdy# is asserted) when another bus master requests the bus, the arbiter can de-assert one grant and assert the next grant during the same pci clock cycle. 13.3.4 secondary bus arbitration using external arbiter the internal arbiter can be disabled by pulling the secondary bus internal arbiter enable pin (s_cfn#) high. an external arbiter must be used if more than one bus master is required to initiate cycles on the secondary bus. when s_cfn# is tied high, the pci 6150 re-configures two pins to be external request and grant pins. s_req0# is re-configured to be the external request output from the pci 6150 and is used by the pci 6150 to request the secondary bus. s_gnt0# is reconfigured to be the pci 6150 external grant input from the external arbiter. if the pci 6150 requests the secondary pci bus (s_req0# asserted) and the external arbiter grants the bus to the pci 6150 (s_gnt0# asserted), the pci 6150 initiates a transaction on the secondary bus one clock cycle later. if the secondary bus external arbiter asserts s_gnt0# when s_req0# is not asserted, the pci 6150 parks s_ad[31:0], s_cbe[3:0]#, and s_par by driving these signals to valid logic levels. when using an external arbiter, the unused secondary bus grant outputs (s_gnt[8:1]#) are driven high. unused secondary bus request inputs (s_req[8:1]#) must be pulled high. section 13 pci bus arbitration arbitration bus parking pci 6150bb data book, version 2.11 13-4 ? 2005 plx technology, inc. all rights reserved. 13.4 arbitration bus parking bus parking refers to driving the ad[31:0], cbe[3:0]#, and par lines to a known value while the bus is idle. the pci bus is parked on the pci 6150 primary or secondary bus when one or both buses are idle. bus parking occurs when the bus grant to the pci 6150 on the parked bus is being asserted, and the pci 6150 request for that bus is not asserted. the ad[31:0] and cbe[3:0]# signals are first driven low (0), then the par signals are driven low (0) one cycle later. when the gnt# signal for the parked bus is de-asserted, the pci 6150 places the ad[31:0], cbe[3:0]#, and par signals into a high-impedance state on the next pci clock cycle. if the pci 6150 is parking and wants to initiate a transaction on that bus, the pci 6150 can start the transaction on the next pci clock cycle by asserting frame# if gnt# remains asserted. if the secondary bus internal arbiter is enabled, the secondary arbiter can be optionally parked at the last active slot, or on any of the designated slots, and it can also be disabled. the pci 6150 has the following options related to arbitration parking, selectable through internal arbiter control register bus grant parking control bits (iacntrl[15:12]; pci:50h): no parking ?all grants are de-asserted if there are no asserted requests fixed parking ?grant can be assigned to a specific master last master granted ?grant is assigned to the last granted master pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 14-1 14?gpio interface 14 gpio interface this section describes the gpio interface pins, control registers, and serial stream. 14.1 gpio interface pins the pci 6150 provides four, general-purpose i/o interface pins (gpio[3:0]). (refer to table 14-1.) during normal operation, the configuration registers control the gpio interface. during secondary reset, the gpio[2:0] and msk_in can be used to shift in a 16-bit serial stream that serves as a secondary bus clock disable mask. the gpio[3:0] pins have weak internal pull-up resistors. external pull-up or pull-down resistors are recommended. note: msk_in is used in the pqfp package only. if using the pbga package, use software to disable unused secondary clock buffers through the sclkcntrl; pci:68h register. 14.2 gpio serial stream refer to section 4.3.1, ?secondary clock control,? on page 4-1. 14.3 gpio control registers the gpio registers can be accessed from both sides of the bus. during normal operation, the gpio interface is controlled by the following three gpio configuration registers: output enable (gpiooe) output data (gpiood) input data (gpioid) the gpio configuration registers consist of five 8-bit fields: output enable write 1 to set (gpiooe[7:4]) output enable write 1 to clear (gpiooe[3:0]) output data write 1 to set (gpiood[7:4]) output data write 1 to clear (gpiood[3:0]) input data (gpioid[7:4]) the output enable fields control whether the gpio signals are inputs or outputs. each signal is independently controlled by a bit in each output enable field. if 1 is written to the write 1 to set field, the corresponding pin is activated as an output. if 1 is written to the write 1 to clear field, the output driver is placed into a high-impedance state, and the pin is input only. writing zeros (0) to these registers has no effect. the reset state for these signals is input only. the output data fields also use the write 1 to set and clear methods. if 1 is written to the write 1 to set field and the pin is enabled as an output, the corresponding gpio output is driven high. if 1 is written to the write 1 to clear field and the pin is enabled as an output, the corresponding gpio output is driven low. writing zeros (0) to these registers has no effect. the value written to the output data register is driven only when the gpio signal is configured as output. a type 0 configuration write operation is used to program these registers. the reset value for the output is 0. the input data field is read-only and reflects the current value of the gpio[3:0] pins. a type 0 configuration read operation to the input data register returns the values of these pins. the gpio[3:0] pins can be read at any time, whether configured as input only or bi-directional. table 14-1. gpio pin operation gpio pin alternate function gpio0?pull-up functions as secondary bus clock mask shift register clock output when p_rstin# is asserted at 66 mhz maximum frequency. gpio1?pull-up no alternate function. gpio2 ?pull-up functions as shift/load control output to shift register when p_rstin# is asserted. values: 0 = load 1 = shift gpio3 ?pull-up when gpio3fn# is tied high, gpio3 functions as a gpio pin regardless of eject_en# state. gpio3 functions as ejector input only when both gpio3fn# and eject_en# are tied low (hot swap enabled). pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 15-1 15?supported commands 15 supported commands this section discusses the pci 6150 pci command set. 15.1 primary interface command set table 15-1 delineates the pci 6150 primary interface command set. table 15-1. primary interface supported commands p_cbe[3:0]# pci command support 0000b interrupt acknowledge not supported. 0001b special cycle 0010b i/o read if the address is within pass-through i/o range, the transaction is claimed and passed through. if the address points to an i/o-mapped internal bridge register, the transaction is claimed. otherwise, the transaction is ignored. 0011b i/o write same as i/o read (p_cbe[3:0]#=0010b). 0100b ? 0101b reserved ? 0110b memory read if the address is within pass-through memory range, the transaction is claimed and passed through. if the address points to a memory-mapped internal bridge register, the transaction is claimed. otherwise, the transaction is ignored. 0111b memory write same as memory read (p_cbe[3:0]#=0110b). 1000b ? 1001b reserved not supported. 1010b configuration read type 0 configuration read, claimed if the p_idsel line is asserted; otherwise, the read is ignored. if claimed, the target internal register(s) is read. never passed through. type 1 configuration read, claimed if the p_idsel line is asserted; otherwise, the read is ignored. if the target bus is the bridge?s se condary bus, the transacti on is claimed and passed through as a type 0 configuration read. if the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus), the transaction is claimed and passed through as a type 1 configuration read. 1011b configuration write type 0 configuration write, same as configuration read (p_cbe[3:0]#=1010b). type 1 configuration write (not special cy cle request), same as configuration read (p_cbe[3:0]#=1010b). configuration write as special cycle request (d evice = 1fh, function = 7h). if the target bus is the bridge?s secondary bus, the transacti on is claimed and passed through as a special cycle. if the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus), the transaction is cl aimed and passed through unchanged as a type 1 configuration write. section 15 supported commands primary interface command set pci 6150bb data book, version 2.11 15-2 ? 2005 plx technology, inc. all rights reserved. 1100b memory read multiple treated as a memory read (p_cbe[3:0]#=0110b). 1101b dac not supported. 1110b memory read line treated as a memory read (p_cbe[3:0]#=0110b). 1111b memory write and invalidate treated as a memory write (p_cbe[3:0]#=0111b). table 15-1. primary interface supported commands (continued) p_cbe[3:0]# pci command support section 15 secondary interface command set supported commands pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 15-3 15?supported commands 15.2 secondary interface command set table 15-2 delineates the pci 6150 secondary interface pci command set. table 15-2. secondary interface supported commands s_cbe[3:0]# pci command support 0000b interrupt acknowledge not supported. 0001b special cycle 0010b i/o read if the address is within pass-through i/o r ange, the transaction is claimed and passed through. if the address points to an i/o-mapped internal bridge register, the transaction is claimed. otherwise, the transaction is ignored. 0011b i/o write same as i/o read (s_cbe[3:0]#=0010b). 0100b ? 0101b reserved ? 0110b memory read if the address is within pass-through memory r ange, the transaction is claimed and passed through. if the address points to a memory-mapped inte rnal bridge register, the transaction is claimed. otherwise, the transaction is ignored. 0111b memory write same as memory read (s_cbe[3:0]#=0110b). 1000b ? 1001b reserved not supported. 1010b configuration read upstream configuration read cycles. not supported. 1011b configuration write type 0 configuration write. not supported. type 1 configuration write (not a special cycle request). not supported. configuration write as special cycle request (d evice = 1fh, function = 7h). if the target bus is the bridge?s primary bus, the transaction is claimed and passed through as a special cycle. if the target bus is neither t he primary bus nor in the range of buses defined by the bridge?s secondary and subordinate bus registers, t he transaction is claimed and passed through unchanged as a type 1 configuration write. if the target bus is not the bridge?s primary bus , but is within the range of buses defined by the bridge?s secondary and subordinate bus registers, the transaction is ignored. 1100b memory read multiple treated as a memory read (s_cbe[3:0]#=0110b). 1101b dac not supported. 1110b memory read line treated as a memory read (s_cbe[3:0]#=0110b). 1111b memory write and invalidate treated as a memory write (s_cbe[3:0]#=0111b). pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 16-1 16?bridge behavior 16 bridge behavior this section presents various bridge behavior scenarios that occur when the target responds to a cycle generated by the pci 6150, on behalf of the initiating master. 16.1 bridge actions for various cycle types a pci cycle is initiated by frame# assertion. in a bridge, there are several possibilities for this to occur. table 16-1 summarizes these possibilities, and delineates the pci 6150 action for various cycle types. after the pci cycle is initiated, a target then has up to three clocks to respond before subtractive decoding, or four clocks before a master abort, is initiated. if the target detects an address hit, it asserts devsel# in the cycle corresponding to the configuration status register devsel# timing bits (pcisr[10:9]; pci:06h or pcissr[10:9]; pci:1eh). pci cycle termination can occur in a number of ways. normal termination begins by the initiator (master) de-asserting frame#, with irdy# being asserted (or remaining asserted) on the same cycle. the cycle completes when trdy# and irdy# are simultaneously asserted. the target should de-assert trdy# for one cycle following final assertion (sustained three-state signal). table 16-1. bridge actions for various cycle types initiator target pci 6150 response master on primary port target on the same primary port does not respond. this situation is detected by decoding the address and monitoring p_devsel# for other fast and medium-speed devices on the primary port. target on secondary port asserts p_devsel# and normally terminates the cycle if posted; otherwise, returns with a retry. next, passes the cycle to the appropriate port. when the cycle completes on the target port, the pci 6150 waits for the initiator to repeat the same cycle and end with normal termination. target not on primary nor secondary port does not respond and the cycle terminates as a master abort. master on secondary port target on the same secondary port does not respond. target on primary or other secondary port asserts s_devsel# and normally terminates the cycle if posted; otherwise, returns with a retry. next, passes the cycle to the appropriate port. when the cycle completes on the target port, the pci 6150 waits for the initiator to repeat the same cycle and end with normal termination. target not on primary nor other secondary port does not respond. section 16 bridge behavior abnormal termination (m aster abort, initiated by bridge master) pci 6150bb data book, version 2.11 16-2 ? 2005 plx technology, inc. all rights reserved. 16.2 abnormal termination (master abort, initiated by bridge master) a master abort indicates that the pci 6150, operating as a master, receives no response from a target ( that is , no target asserts p_devsel# or s_devsel#). the bridge de-asserts frame#, then de-asserts irdy#. 16.3 parity and error reporting parity must be checked for all addresses and write data. parity is defined on the p_par and s_par signals. parity should be even [ that is , an even number of ones (1)] across ad[31:0], cbe[3:0]#, and par. parity information on par is valid the cycle after ad[31:0] and cbe[3:0]#, are valid. for all address phases, if a parity error is detected, the error is reported on the p_serr# signal by asserting p_serr# for one cycle, then placing two cycles into a high-impedance state after the bad address. p_serr# can be asserted only if the command register p_serr# and parity error response bits are both set to 1 (pcicr[8, 6]=11b; pci:04h, respectively). for write data phases, a parity error is reported by asserting p_perr# two cycles after the data phase and remains asserted for one cycle when pcicr[8]=1. the target reports any type of data parity errors during write cycles, while the master reports data parity errors during read cycles. address parity error detection causes the pci bridge target to not claim the bus (p_devsel# remains inactive). the cycle then terminates with a master abort. when the bridge is operating as master, a data parity error during a read cycle results in the bridge master initiating a master abort. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 17-1 17?pci flow-through optimization 17 pci flow-through optimization this section describes flow-through optimization, including precautions when using non-optimized pci master devices, posted write and delayed read flow through, read cycle optimization, and read prefetch boundaries. 17.1 overview the pci 6150 operates in flow-through mode when data from the same transaction is simultaneously transferred on both sides of the bridge ( that is , data on one side of the bridge ?flows through? to the other side of the bridge). the pci 6150 has several options to optimize pci transfers after flow-though mode is achieved by way of the bridge. the purpose of flow-through mode is to improve pci bus utilization and efficiency. if data transfers on one side of the bridge are broken into several transactions on the other side of the bridge, poor bus efficiency results. by using flow-through mode, the pci 6150 improves bus efficiency for posted writes, delayed reads, and reads to prefetchable spaces. 17.2 precautions when using non-optimized pci master devices the pci 6150 is capable of high-performance prefetching. however, some pci masters may be unable to prefetch a large amount of data. this may be due to a small internal buffer size or other limiting factors. for example , if data is being read from a register or fifo-based architecture, valuable data may be lost if the host prematurely terminates a prefetch cycle (ideally such spaces would not be listed as prefetchable). under these circumstances the default values for prefetching may be overly aggressive and affect overall performance. in this case, tune default prefetching by reprogramming the prefetch registers, as listed in table 17-1. (refer to section 6, ?registers,? for a detailed description of these registers.) the serial eeprom can also be used to program the configuration space upon reset. 17.3 posted write flow through during flow through of posted write cycles, if there is only one data transfer pending in the internal post memory write queue, the pci 6150 can be programmed to wait for a specified number of clocks before disconnecting. the pci 6150 de-asserts irdy# on the target side and waits up to seven clocks for additional data from the initiator. if new write data is received from the initiator during this period, the pci 6150 re-asserts irdy# and continues with the write cycle. if new write data is not received during this period, the pci 6150 terminates the cycle to the target with the last data from the queue and later finishes the cycle. the flow-through control registers for posted writes are detailed in section 6, ?registers.? (refer to pftcr[2:0]; pci:44h and sftcr[2:0]; pci:4eh.) 17.4 delayed read flow through for flow through of delayed read cycles, if the internal read queue is almost full, the pci 6150 can be programmed to insert wait states to delay read data from the target for a specified number of clocks before disconnecting. during this time, the pci 6150 de-asserts irdy# on the target bus and waits up to seven clocks. if additional space becomes available in the internal read queue before the end of the irdy# inactive period, the pci 6150 re-asserts irdy# and proceeds with the next read data phase. if no additional space becomes available in the internal read queue, the current data phase becomes the last (irdy# is asserted) and the cycle disconnects at the end of the data phase. the flow-through control registers for delayed reads are detailed in section 6, ?registers.? (refer to pftcr[6:4]; pci:44h and sftcr[6:4]; pci:4eh.) section 17 pci flow-through optimization read cycle optimization pci 6150bb data book, version 2.11 17-2 ? 2005 plx technology, inc. all rights reserved. 17.5 read cycle optimization the main function of read cycle optimization is to increase the probability of flow through occurring during read accesses to prefetchable memory regions. to improve the probability of flow through, the amount of data to be prefetched must be correctly configured. if the pci 6150 prefetches insufficient data, flow through does not occur because prefetching on the target side completes before the initiator retries the read access. under these circumstances, the read cycles become divided into multiple cycles. if the pci 6150 prefetches excessive data and the internal fifos fill, the pci 6150 must wait for the initiator to retry the previous read cycle and then flush the unclaimed data before queuing subsequent cycles. the initial count is normally equivalent to the cache- line size. this assumes that a master usually requires at least one cache line of data. the incremental count is used only when the pci 6150 does not detect flow through for the current cycle being prefetched during the initial prefetch count. the pci 6150 continues prefetching in increments until it reaches the maximum count, then disconnects the cycle. for read prefetching, the pci 6150 implements several registers that control the amount of data prefetched on the primary and secondary pci buses. the prefetch registers listed in table 17-1 can be used to optimize pci 6150 performance during read cycles. the pci 6150 prefetches until flow through occurs or prefetching must stop, based on the following conditions: prefetch continues while: (ipmc + ipc + ipc + ? + ipc) < mpc where: ipmc = initial prefetch maximum count ipc = incremental prefetch count, < ? mpc mpc = maximum prefetch count if the prefetch count did not reach mpc and flow through was achieved, the pci 6150 continues prefetching until the requesting master terminates the prefetch request. otherwise, when mpc is reached, the pci 6150 stops prefetching data. incremental prefetch can be disabled by setting ipc mpc. 17.5.1 primary and secondary initial prefetch count assuming that there is sufficient space in the internal fifo, the primary and secondary initial prefetch count registers (pitlpcnt; pci:48h and sitlpcnt; pci:49h, respectively) control the amount of data initially prefetched by the pci 6150 on the primary or secondary bus during reads to the prefetchable memory region. if flow through is achieved during this initial prefetch, the pci 6150 continues prefetching beyond this count. table 17-1. reprogramming prefetch registers configuration space register data primary initial prefetch count (pitlpcnt; pci:48h) same value as cache line size register (pciclsr; pci:0ch). note: most pcs set this value to 08h. secondary initial prefetch count (sitlpcnt; pci:49h) primary incremental prefetch count (pincpcnt; pci:4ah) 0h secondary incremental prefetch count (sincpcnt; pci:4bh) primary maximum prefetch count (pmaxpcnt; pci:4ch) secondary maximum prefetch count (smaxpcnt; pci:4dh) section 17 read prefetch boundaries pci flow-through optimization pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 17-3 17?pci flow-through optimization 17.5.2 primary and secondary incremental prefetch count the primary and secondary incremental prefetch count registers (pincpcnt; pci:4ah and sincpcnt; pci:4bh, respectively) control the amount of prefetching after the initial prefetch. if flow through is not achieved during the initial prefetch, the pci 6150 attempts to prefetch further data, until the fifo fills, or until the maximum prefetch count is reached. each subsequent prefetch is equal to the incremental prefetch count. 17.5.3 primary and secondary maximum prefetch count the primary and secondary maximum prefetch count registers (pmaxpcnt; pci:4ch and smaxpcnt; pci:4dh, respectively) limit the amount of prefetched data for a single entry available in the internal fifo at any time. during read prefetch cycles, the pci 6150 disconnects the cycle if the data count in the fifo for the current cycle reaches this value, and flow through has not been achieved. 17.6 read prefetch boundaries for memory read and memory read line commands, the pci 6150 prefetches from the starting address up to an address with an offset that is a multiple of the initial prefetch count. for example , if the starting address is 10h and the initial prefetch count equals 20h, the pci 6150 prefetches only a 10h (20h to 10h) count. after this, the pci 6150 begins incremental prefetch until the maximum prefetch count is reached, or flow through is achieved. the exception to this is in the case of a 64-bit request and six or fewer dwords from the boundary, or a 32-bit request and four or fewer dwords from the boundary, in which the pci 6150 does not activate incremental prefetch. for memory read multiple commands, if the starting address is not 0, the pci 6150 first prefetches from the starting address up to the address with an offset equal to that of the initial prefetch count. after this, the pci 6150 prefetches one additional initial prefetch count. for example , if the starting address is 10h and the initial prefetch count equals 20h, the pci 6150 first prefetches a 10h (20h to 10h) count, then continues to prefetch another 20h count. subsequent to this, incremental prefetch is invoked until the maximum prefetch count is reached or flow through is achieved. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 18-1 18?power management 18 power management this section describes the power management feature. 18.1 overview the pci 6150 incorporates functionality that meets the requirements of pci power mgmt. r1.1 . these features include: pci power management registers, using the enhanced capabilities port (ecp) address mechanism support for d 0 , d 3cold , and d 3hot power management states support for d 0 , d 1 , d 2 , d 3cold , and d 3hot power management states for devices behind the bridge support for b 2 secondary bus power state when in the d 3hot power management state 18.2 power management transitions table 18-1 delineates the states and related actions the pci 6150 performs during power management transitions. (no other transactions are allowed.) pme# signals are routed from downstream devices around pci-to-pci bridges. pme# signals do not pass through pci-to-pci bridges. table 18-1. states and related actions during power management transitions current state next state action d 0 d 1 unimplemented power state. the pci 6150 ignores the write to the power state bits (power state remains at d 0 , pmcsr[1:0]=00b; pci:e0h). d 0 d 2 d 0 d 3hot if enabled by the bpcc_en pin, the pci 6150 disables the secondary clocks and drives them low. d 0 d 3cold power is removed from the pci 6150. a power-up reset must be performed to bring the pci 6150 to d 0 . d 3cold d 0 power-up reset. the pci 6150 performs the standard power-up reset functions. d 3hot d 0 the pci 6150 enables secondary clock outputs and performs an internal chip reset. s_rstout# is not asserted. all registers are returned to the reset values and buffers are cleared. d 3hot d 3cold power is removed from the pci 6150. a power-up reset must be performed to bring the pci 6150 to d 0 . pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 19-1 19?hot swap 19 hot swap this section describes the hot swap feature and its use. 19.1 overview the pci 6150 incorporates functionality that meets picmg 2.1 r2.0 requirements with high-availability programming interface level 1 (pi=1). the compactpci hot swap register block is located at pci configuration offset e4h. refer to picmg 2.1 r2.0 for detailed implementation guidelines. the hot insertion power-up sequence recommendation is illustrated in figure 19-1. notes: to use the hot swap function, eject_en# and gpio3fn# must be connected to 0. (refer to table 19-1.) if the hot swap function is not used, pull gpio3fn# high or gpio3 low to disable the function. 19.2 led on/off (pi=1) for pi=1 support, upon rstin# assertion, the pci 6150 turns on the led. after rstin# de-assertion, the led remains on until the eject switch (handle) is closed, then the pci 6150 turns off the led. figure 19-1. hot insertion power-up sequence recommendation table 19-1. eject_en# and gpio3fn# settings for enabling hot swap capability eject_en# gpio3fn# hot swap eject input 0 0 enabled gpio3 don?t care 1 disabled ? inactive active in high-impedance state normal pci bus state eject handle open eject handle closed p_clkin, s_clkin eject pci bus buffers p_rstin#, s_rstout# gpio3 section 19 hot swap hot swap signals pci 6150bb data book, version 2.11 19-2 ? 2005 plx technology, inc. all rights reserved. 19.3 hot swap signals the pci 6150 uses the following hot swap-related pins: eject_en# ?ejector pin use enable. used to enable the gpio3 pin as eject input. if this pin is 1, gpio3 functions as a gpio pin. gpio3 only functions as eject input when both gpio3fn# and eject_en# are tied low, which also enables hot swap capability. enum# ?indicates an open-drain bused signal asserted when an adapter was inserted or is ready to be extracted from a pci slot. asserted through the hot swap registers (hs_cntl; pci:e4h, hs_csr; pci:e6h, and hs_next; pci:e5h). gpio3fn# ?when gpio3fn# is tied high, gpio3 functions as a gpio pin regardless of the eject_en# pin state. gpio3 functions as ejector input only when both gpio3fn# and eject_en# are tied low. to enable hot swap capability, both the gpio3fn# and eject_en# inputs must be low. pin_led/eject ?active high signal that allows other circuits to drive the blue hot swap led. turns on led if rstin# is asserted, or when the loo bit is set (hs_csr[3]=1; pci:e6h) and rstin# is de-asserted. 19.4 hot swap register control and status the pci 6150 hot swap control/status register (hs_csr) is located at pci offset e6h. 19.5 device hiding the pci 6150 implements device hiding to eliminate mid-transaction extractions. this invokes device hiding by hardware from the hot swap port after rstin# becomes inactive and the ejector handle remains unlocked. software quiesces the pci 6150 when device hiding is invoked. the current transaction is completed as early as possible. the pci 6150 does not initiate a transaction as a master, respond as a target to i/o transactions, nor signal interrupts. when device hiding is invoked, the pci 6150 terminates the current configuration transaction by signaling a disconnect. after the current transaction completes (is disconnected), the pci 6150 does not respond as a target to any subsequent transactions until device hiding is canceled. if not participating in a transaction when device hiding is invoked, the pci 6150 does not respond as a target to subsequent transactions until device hiding is canceled. device hiding is canceled when the handle switch is relocked. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 20-1 20?vpd 20 vpd this section describes the vpd feature. the pci 6150 contains the vital product data (vpd) registers, as specified in pci r2.3 . vpd information is stored in the serial eeprom device, along with autoload information. the pci 6150 provides storage of 192 bytes of vpd data in the serial eeprom device. the vpd register block is located at offsets e8h to efh in pci configuration space. (refer to section 6.1.2.15, ?vpd capability.?) vpd also uses the enhanced capabilities port address mechanism. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 21-1 21?testability/debug 21 testability/debug this section describes the jtag interface for use in testing and debugging the pci 6150. 21.1 jtag interface the pci 6150 provides a jtag boundary scan interface, which can be utilized to debug a pin?s board connectivity. 21.1.1 ieee 1149.1 test access port the ieee 1149.1 test access port (tap), commonly called the jtag (joint test action group) debug port, is an architectural standard described in ieee standard 1149.1-1990, ieee standard test access port and boundary-scan architecture. the standard describes a method for accessing internal chip facilities using a four- or five-signal interface. the jtag debug port, originally designed to support scan-based board testing, is enhanced to support the attachment of debug tools. the enhancements, which comply with ieee standard 1149.1-1990 specifications for vendor-specific extensions, are compatible with standard jtag hardware for boundary-scan system testing. jtag signals ?jtag debug port implements the four required jtag signals?tck, tdi, tdo, tms?and the optional trst# signal. (refer to table 3-10, ?jtag pins,? on page 3-15 for signal descriptions.) jtag clock requirements ?tck signal frequency can range from dc to 10 mhz. jtag reset requirements ?jtag debug port logic and system simultaneously reset. the two methods for placing the pci 6150 jtag tap controller into the test-logic-reset state are as follows: upon receiving trst#, the jtag tap controller returns to the test-logic reset state hold the pci 6150 tms pin high while transitioning the pci 6150 tck pin five times 21.1.2 jtag instructions the jtag debug port provides the standard extest , sample/preload , and bypass instructions. invalid instructions behave as bypass instructions. table 21-1 lists the jtag instructions, along with their input codes. table 21-1. jtag instructions (ieee standard 1149.1-1990) instruction input code extest 00000b sample/preload 00001b bypass 11111b section 21 testability/debug jtag interface pci 6150bb data book, version 2.11 21-2 ? 2005 plx technology, inc. all rights reserved. 21.1.3 jtag boundary scan boundary scan description language (bsdl), ieee 1149.1b-1994, is a supplement to ieee standard 1149.1-1990 and ieee 1149.1a-1993, ieee standard test access port and boundary-scan architecture . bsdl, a subset of the ieee 1076-1993 standard vhsic hardware description language (vhdl), allows a rigorous description of testability features in components that comply with the standard. automated test pattern generation tools use bdsl for package interconnect tests and electronic design automation (eda) tools for synthesized test logic and verification. bsdl supports robust extensions that can be used for internal test generation and to write software for hardware debug and diagnostics. the primary components of bsdl include the logical port description, physical pin map, instruction set, and boundary register description. the logical port description assigns symbolic names to the pci 6150 pins. each pin has a logical type of in, out, in out, buffer, or linkage that defines the logical signal flow direction. the physical pin map correlates the pci 6150 logical ports to the physical pins of a specific package. a bsdl description can have several physical pin maps; each map is provided a unique name. instruction set statements describe the bit patterns that must be shifted into the instruction register to place the pci 6150 in the various test modes defined by the standard. instruction set statements also support instruction descriptions unique to the pci 6150. the boundary register description lists each of its cells or shift stages. each cell has a unique number?the cell numbered 0 is the closest to the test data out (tdo) pin and the cell with the highest number is closest to the test data in (tdi) pin. each cell contains additional information, including: cell type logical port associated with the cell logical function of the cell safe value control cell number disable value result value 21.1.4 jtag reset input trst# the trst# input pin is the asynchronous jtag logic reset. trst# assertion causes the pci 6150 tap controller to initialize. in addition, when the tap controller is initialized, it selects the pci 6150 normal logic path (core-to-i/o). consider the following when implementing the asynchronous jtag logic reset on a board: if jtag functionality is required, one of the following should be considered: use the trst# input signal low-to-high transition once. hold the pci 6150 tms pin high while transitioning the pci 6150 tck pin five times. if jtag functionality is not required, the trst# signal must be directly connected to ground. note: ieee standard 1149.1-1990 requires pull-up resistors on the tdi, tms, and trst# pins. to remain pci r2.3-compliant, no internal pull-up resistors are provided on jtag pins in the pci 6150; therefore, the pull-up resistors must be externally added to the pci 6150 when implementing jtag. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 22-1 22?mechanical specs 22 mechanical specs this section provides the pci 6150 mechanical dimensions and pinout. the pci 6150 is available as an industry standard 208-pin pqfp or 256-pin pbga package. section 22 mechanical specs 208-pin pqfp pci 6150bb data book, version 2.11 22-2 ? 2005 plx technology, inc. all rights reserved. 22.1 208-pin pqfp 22.1.1 mechanical dimensions?208-pin pqfp figure 22-1 illustrates the mechanical dimensions of the 208-pin pqfp package. table 22-1 lists the mechanical dimensions, in millimeters, unless specified otherwise. figure 22-1. pci 6150 mechanical dimensions?208-pin pqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 47 46 48 49 50 51 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 110 111 109 108 107 106 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 52 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 p2 157 53 105 104 w1 w2 w3 p1 h1 h2 n f l d c topside view cross-section view section 22 208-pin pqfp mechanical specs pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 22-3 22?mechanical specs table 22-1. pci 6150 mechanical dimensions fo r figure 22-1 symbols (in millimeters)?208-pin pqfp symbol dimension minimum nominal maximum w1 ? ? ? ? w2 package width (length) 27.95 28.00 28.05 w3 package overall width (length) ? 30.60 ? p1 lead pitch ? 0.50 ? p2 lead width 0.17 ? 0.27 c lead thickness 0.09 ? 0.20 d ? ? 0.13 ? h1 package overall height ? 4.20 ? h2 package thickness 3.17 ? 3.95 l lead length ? 1.30 ? f foot length 0.45 0.60 0.75 n foot angle 0 ? 7 section 22 mechanical specs 208-pin pqfp pci 6150bb data book, version 2.11 22-4 ? 2005 plx technology, inc. all rights reserved. 22.1.2 physical layout with pinout?208-pin pqfp figure 22-2. pci 6150 top view?208-pin pqfp pci 6150 208 207 201 202 203 206 204 205 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 174 175 173 172 171 170 169 168 167 165 166 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 28 vdd s_req 0# s_ad28 vdd s_ad29 s_ad31 s_ad30 vss s_ad27 vss s_ad26 s_ad25 vdd s_ad2 4 s_cbe3# vss s_ad23 s_ad22 vdd s_ad21 s_ad20 vss s_ad19 s_ad18 vdd s_ad17 s_ad1 6 vss s_cbe2# s_frame# vdd s_irdy# s_trdy# vss s_devsel # s_stop# s_lock# s_perr# vdd s_serr# s_par s_cbe1# s_ad15 vss s_ad14 vdd s_ad13 s_ad12 eepdat a s_ad11 eepcl k vdd vss gpio3fn# s_ad10 s_m66en s_ad9 reserved s_ad8 s_cbe0# vss s_ad7 s_ad6 vdd s_ad5 s_ad 4 vss s_ad3 s_ad2 vdd s_ad1 s_ad0 vss s_vio trst# tck tms vdd tdo tdi pin_led/eject enum# msk_in cfg66 p_vio vss p_ad0 p_ad1 vdd p_ad2 p_ad3 vss p_ad4 p_ad5 vdd p_ad6 p_ad7 vss p_cbe0# p_ad8 vdd p_ad9 eject_en# vdd vss oscsel# s_req1# p_ad30 p_ad31 vss p_req# p_gnt# p_clkin bpcc_en p_rstin# s_clko9 s_clko8 vdd s_clko7 s_clko6 vss s_clko5 s_clko4 vdd s_clko3 s_clko2 vss s_clko1 s_clko0 gpio1 vdd gpio2 gpio3 s_cfn# s_rstout# s_clkin vss s_gnt8# s_gnt7# s_gnt6# s_gnt5# s_gnt4# s_gnt3# s_gnt2# vss s_gnt1# s_gnt0# s_req8# s_req7# s_req6# s_req5# s_req4# s_req3# s_req2# vdd gpio0 vss p_m66en oscin ee_en # p_ad10 vss p_ad11 p_ad12 p_ad13 vdd vss p_ad15 p_cbe1# p_ad14 p_par p_serr# vd d p_lock# vss p_perr # p_devsel# p_trdy# p_stop# p_irdy# p_frame # p_cbe2 # vss p_ad16 p_ad17 vdd p_ad19 p_ad18 vss p_ad20 p_ad21 vdd p_ad22 p_ad23 vss p_idsel p_cbe3# p_ad24 vdd p_ad25 p_ad26 vss p_ad27 p_ad28 vdd p_ad29 vdd vdd section 22 256-pin pbga mechanical specs pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 22-5 22?mechanical specs 22.2 256-pin pbga 22.2.1 mechanical dimensions?256-pin pbga figure 22-3 illustrates the mechanical dimensions of the 256-pin pbga package. figure 22-3. pci 6150 mechanical dimensions?256-pin pbga topside view cross-section view underside view dimensions in millimeters (mm) a1 ball pad corner a1 ball pad corner section 22 mechanical specs 256-pin pbga pci 6150bb data book, version 2.11 22-6 ? 2005 plx technology, inc. all rights reserved. 22.2.2 physical layout with pinout?256-pin pbga figure 22-4. pci 6150 top view?256-pin pbga 12345678910111213141516 a vss s_req2# vdd s_ad31 s_ad28 s_ad25 s_ad22 s_ad19 s_ad17 s_frame# s_devsel# s_perr# s_par s_ad13 s_ad11 vss a b vss vss s_req1# s_req0# s_ad27 s_cbe3# s_ad21 s_ad18 s_cbe2# s_irdy# s_stop# s_cbe1# s_ad12 gpio3fn# vss s_ad10 b c s_req5# s_req4# vss vdd s_ad29 s_ad24 s_ad23 s_ad20 s_ad16 s_trdy# s_lock# s_ad15 vss eepclk ee_en# s_ad8 c d s_gnt0# s_req6# s_req3# vss s_ad30 s_ad26 vdd vdd vdd vdd s_serr# s_ad14 vss eepdata s_m66en s_ad6 d e s_gnt3# s_gnt2# s_req7# s_req8# vss vdd vdd vdd vdd vdd vdd vss s_ad9 s_ad7 s_cbe0# s_ad4 e f s_gnt7# s_gnt6# s_gnt1# s_gnt4# vdd vss vss vss vss vss vss vdd s_ad5 s_ad3 s_ad2 s_ad1 f g s_gnt8# vss s_gnt5# vdd vdd vss vss vss vss vss vss vdd vdd s_vio trst# s_ad0 g h s_rstout# s_cfn# s_clkin vdd vdd vss vss vss vss vss vss vdd vdd tms tck tdo h j gpio1 gpio2 gpio3 vdd vdd vss vss vss vss vss vss vdd vdd enum# tdi pin_led/ eject j k gpio0 s_clko0 s_clko1 vdd vdd vss vss vss vss vss vss vdd vdd p_vio oscin oscsel# k l s_clko2 s_clko3 s_clko5 s_clko6 vdd vss vss vss vss vss vss vdd p_ad4 p_ad2 p_ad1 p_ad0 l m s_clko4 s_clko8 s_clko9 p_clkin vss vdd vdd vdd vdd vdd vdd vss p_ad6 p_ad7 p_ad5 p_ad3 m n s_clko7 bpcc_en p_ad31 vss p_ad28 p_ad25 vdd vdd vdd vdd p_par p_ad11 vss vss p_ad8 p_cbe0# n p p_rstin# p_req# vss vss p_ad27 p_idsel p_ad22 p_ad18 p_frame# p_devsel# p_serr# p_ad14 vdd vss vdd p_ad9 p r p_gnt# vss vdd vss p_ad24 p_cbe3# p_ad20 p_ad17 p_cbe2# p_trdy# p_lock# p_ad15 p_ad12 p_m66en vss eject_en# r t vss p_ad30 vdd p_ad29 p_ad26 p_ad23 p_ad21 p_ad19 p_ad16 p_irdy# p_stop# p_perr# p_cbe1# p_ad13 p_ad10 vss t 12345678910111213141516 pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. 23-1 23?electrical specs 23 electrical specs this section presents the pci 6150 electrical specifications. 23.1 general electrical specifications the ratings provided in this subsection are those above which the useful life of the pci 6150 may be impaired. table 23-1 lists the pci 6150 maximum ratings. table 23-2 lists the pci 6150 functional operating range. table 23-3 lists the pci 6150 dc electrical characteristics. caution: stresses greater than the maximums listed in table 23-1 cause permanent damage to the pci 6150. this is a stress rating only and functional operation of the pci 6150 at or above those indicated in the operational sections of this data book is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. note: the power consumption for v dd is dependent on bus frequency, data traffic, and device loading. table 23-1. maximum ratings parameter minimum maximum storage temperature range -55 c +125 c junction temperature ? +125 c v dd supply voltage ?3.9v maximum voltage to signal pins ?5.5v maximum power ? 1.8w table 23-2. functional operating range parameter minimum maximum v dd supply voltage 3.0v 3.6v operating ambient temperature 0 c 70 c table 23-3. dc electrical characteristics symbol parameter condition minimum maximum unit notes v dd v dd supply voltage ?3.03.6v? v io p_v io , s_v io pin interface i/o voltage ?3.05.5v? v ih input high voltage ? 0.5 v dd v io v? v il input low voltage ? -0.5 +0.3 v dd v? v ol output low voltage i iout = +1500 a ? +0.1 v dd v? v oh output high voltage i iout = -500 a 0.9 v dd ?v ? i il input leakage current 0 < v in < v dd ?2a? c in input pin capacitance ? ? 7.0 pf ? section 23 electrical specs pci signal timing specification pci 6150bb data book, version 2.11 23-2 ? 2005 plx technology, inc. all rights reserved. 23.2 pci signal timing specification figure 23-1 illustrates the pci 6150 signal timing specifications. table 23-4 delineates the minimum and maximum values, for the symbols that appear in figure 23-1. figure 23-1. pci signal timing specification v test clk output t val t su t on input t h t off valid valid table 23-4. 66 mhz pci signal timing for figure 23-1 symbol parameter minimum maximum symbol parameter minimum maximum t val clk to signal valid delay? bused signals 2 ns 6 ns t su input setup time to clk? bused signals 3? t val(ptp) clk to signal valid delay? point to point 2 ns 6 ns t su(ptp) input setup time to clk? point to point 5? t on float to active delay 2 ns ? t h input signal hold time from clk 0.5 ? t off active to float delay ? 14 ns v test voltage test ? 0.4 v pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. a-1 a?using pci 6150 a using pci 6150 because the pci 6150 primary and secondary ports are asynchronous to one another, these two independent systems can run at differing frequencies. the secondary bus can be run faster than the primary bus, and vice versa. the pci 6150 controls powerful programmable buffers, which can be used to regulate data throughput for multiple pci masters on the secondary port. the data prefetch size can be programmed to up to 256 bytes. the host system pci bus is connected to the pci 6150 primary port. the secondary pci port can use a custom-designed external arbiter or the pci 6150 internal arbiter. to provide clocks to secondary pci devices and pci 6150 s_clkin, use custom-designed clock generations, pci 6150 s_clko[9:0] outputs (derived out of the primary port pci clock input), or an external oscillator. figure a-1 provides basic optimization design. figure a-1. pci 6150 basic optimization design s-port pci 6150 p-port host system backplane secondary bus pci devices optional secondary clock source input to the pci 6150 can be used for all secondary port pci devices. this clock can be asynchronous and need not be at the same frequency as the host system pci clock input. pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. b-1 b?general information b general information the plx fastlane? pci 6150 32-bit, 66 mhz pci-to- pci bridge is designed for high-performance, high- availability applications in hot swap, bus expansions, programmable data transfer rate control, frequency conversions from slower-to-faster or faster-to-slower pci buses. the pci 6150 provides sophisticated buffer management and configuration options designed to customize performance optimization. the pci 6150 offers the largest data fifo among all 32-bit pci-to-pci bridges in today?s market. the pci 6150 provides the following features and applications: pci r2.3 compliant 3.3v signaling, including 5v input signal tolerance and fast pci buffers provides 1 kb of buffering (data fifo) to maximize performance upstream and downstream posted write buffers (256 bytes each) upstream and downstream read data buffers (256 bytes each) supports up to four simultaneous posted write transactions and four simultaneous delayed transactions in each direction programmable prefetch of up to 256 bytes for maximum read performance optimization flow-through zero wait state burst up to 4 kb for large volume data transfer optional flow-through enable allows for customization fast back-to-back enable?read-only supported asynchronous design supports standard 66-to- 33 mhz and faster secondary port speed, such as 33-to-66 mhz conversion out-of-order delayed transactions enhanced address decoding 32-bit i/o address range 32-bit memory-mapped i/o address range isa aware mode for legacy support in the first 64 kb of i/o address range vga addressing and palette snooping support address stepping hardcoded to two clocks ten secondary clock outputs with pin-controlled enable and individual maskable control to nine bus masters on secondary interface support external arbiter or programmable arbitration for up to nine bus masters on secondary interface support hot swap ready picmg 2.1 r2.0 with pi=1 support for device hiding, eliminating mid-transaction extraction problems pci mobile design guide and power management d 3cold wakeup capable with pme# support four gpio pins with output control and power-up status latch capable serial eeprom loadable and programmable pci read-only register configurations serial eeprom load modification and recheck vpd support ieee standard 1149.1-1990 jtag interface for boundary scan test multiple ids check all device and revision ids industry-standard 208-pin plastic quad flat pack (pqfp) or 256-pin (ball) plastic ball grid array (pbga) package b.1 hint/plx part number conversion table b-1. hint/plx part number conversion hint part number plx part number hb4 pci 6150 appendix b general information package ordering pci 6150bb data book, version 2.11 b-2 ? 2005 plx technology, inc. all rights reserved. b.2 package ordering the pci 6150 is available in standard leaded packaging and lead-free rohs packaging. ordering information is delineated in table b-2. b.3 united states and international representatives, and distributors a list of plx technology, inc., representatives and distributors can be found at http://www.plxtech.com. b.4 technical support plx technology, inc., technical support information is listed at http://www.plxtech.com/support/, or call 408 774-9060 or 800 759-3735. table b-2. available packages package type ordering part numbers standard leaded pqfp package pci6150-bb66pc lead-free rohs green pqfp packaging pci6150-bb66pc g standard leaded pbga package pci6150-bb66bc lead-free rohs green pbga packaging pci6150-bb66bc g pci 6150-bb66pc g pci 6150?family/core pci 6150 device bb?silicon revision 66?speed grade (66 mhz pci bus) p?package type p = plastic quad flat package (pqfp) c?case temperature i = industrial temperature c = commercial temperature es = engineering sample b = plastic ball grid array (pbga) g?lead-free rohs green packaging pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. c-1 c?pin comparisons and signal differences c pci 6150bb and pci 6350aa pin comparisons and signal differences c.1 pin assignme nt comparisons table c-1 lists the pqfp pin differences, and table c-2 lists the pbga pin differences, between the pci 6150bb and pci 6350aa. table c-1. pci 6150bb versus pci 6350aa pin assignment comparison?pqfp package pqfp pin location pci 6150bb pci 6350aa 51 oscsel# v dd 54 oscin v ss 103 ee_en# v dd 106 eject_en# v ss 124 p_v io pme_en# 127 enum# nc 128 pin_led/eject nc 135 s_v io nc 151 reserved ee_en# 155 gpio3fn# v dd table c-2. pci 6150bb versus pci 6350aa pin assignment comparison?pbga package pbga pin location pci 6150bb pci 6350aa b14 gpio3fn# nc g14 s_v io nc j14 enum# nc j16 pin_led/eject nc k14 p_v io nc k15 oscin msk_in k16 oscsel# cfg66 r16 eject_en# nc appendix c pci 6150bb and pci 6350aa pin comparisons and signal differences package signal differences pci 6150bb data book, version 2.11 c-2 ? 2005 plx technology, inc. all rights reserved. c.2 package signal differences table c-3 lists the signals that exist in one pci 6150bb or pci 6350aa package type, but not the other ( that is, in the pqfp, but not the pbga, or, in the pbga, but not the pqfp). table c-3. signal differences between pci 6150bb and pci 6350aa pqfp and pbga packages signal name pci 6150bb pci 6350aa pqfp pbga pqfp pbga cfg66 1 1. used only in the pci 6150bb pqfp and pci 6350aa pqfp and pbga packages . in the pci 6150bb pbga package, the 66 mhz-capable bits are hardwired to 1 (pcisr[5]=1; pci:06h and pc issr[5]=1; pci:1eh) to indicate 66 mhz capability. yes no yes yes msk_in 2 2. used only in the pci 6150bb pqfp and pci 6350aa pqfp and pbga packages. if using the pci 6150bb pbga package, use software to disable unused secondary clock buffers through the sclkcntrl; pci:68h register. yes no yes yes pme_en# 3 3. used only in the pci 6350aa pqfp package. in the pci 6150bb pqfp and pbga and pci 6350aa pbga packages, the power management feature is internally bonded as enabled. n/a n/a yes no reserved yes no n/a n/a pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. index-1 index index a abnormal response 8-16 termination 12-2, 16-2 abort master 3-4, 3-6, 3-7, 6-5, 6-10, 6-16, 6-31, 6-34, 8-9, 8-11, 8-12, 8-13, 8-15, 8-16, 8-18, 11-12, 12-2, 16-1, 16-2 target 3-6, 6-5, 6-10, 6-16, 6-31, 6-34, 8-3, 8-4, 8-7, 8-12, 8-13, 8-14, 8-15, 8-16, 8-18, 11-12, 12-2 access, exclusive 12-1?12-2 acntrl register 6-18, 6-27, 13-1 address decoding 9-1?9-5 arbiter control register 6-1, 6-18, 13-1 arbitration 6-18, 6-27?6-28, 13-1?13-4 architectural boundary scan see ieee standard b bcntrl register 3-13, 4-2, 5-1, 5-2, 6-4, 6-15?6-16, 6-18, 6-20, 8-8, 9-1, 9-2, 9-4, 9-5, 11-1, 11-2, 11-3, 11-4, 11-5?11-12 boundary scan description language 21-2 bpcc_en 3-3, 3-17, 6-38, 18-1 bridge behavior 16-1?16-2 control register 6-1, 6-15?6-16 pci 6000 series 1-1?1-4 supports extension register 6-2, 6-38 bsdl see boundary scan description language buffering 8-5 bus operation, pci 8-1?8-18 c cap_ptr register 6-5, 6-14 ccntrl register 6-17, 8-5 cfg66 3-3, 3-17, 5-1, 6-5, 6-10 chip control register 6-1, 6-17, 8-5 clocking 4-1?4-5 clocking, spread spectrum 5-1 clock-related pins 3-2, 3-11 commands 15-1?15-3 primary 6-1 primary pci register 6-4 read queue 2-1 secondary 3-7 serial eeprom 7-1 compactpci hot swap see hot swap completion delayed read 8-7?8-8 delayed write 10-2 control registers 6-2, 6-17?6-18, 6-20, 6-33, 8-6 controller, test access port (tap) see test access port controller d dac 8-1, 8-2, 15-2, 15-3 dcntrl register 5-1, 5-2, 6-18 deadlock 10-1, 10-2 debug 21-1?21-2 decoding 9-1?9-5 delayed read 8-5, 8-7?8-8, 8-16, 12-1 delayed read or write 3-6, 6-19, 6-21, 6-26, 6-31, 6-34, 8-2, 8-4, 8-5, 8-7?8-8, 8-12, 8-15, 8-17, 8-18, 10-1, 10-2, 10-2?10-3, 11-3, 11-4?11-11, 11-12 device hiding 6-39, 19-2 device-specific registers 6-17?6-41, 11-1, 11-3 diagnostic control register 5-2, 6-1, 6-18 dual address cycle see dac e ecp 18-1 ee_en# 3-3, 3-16, 7-1, 7-2 eepaddr register 6-30, 7-1 eepclk 3-3, 3-16, 7-1 eepcntrl register 6-30, 7-1 eepdata pin 3-3, 3-16, 7-1 eepdata register 6-30, 7-1 eject_en# 3-14, 19-1, 19-2 electrical specs 23-1?23-2 emi emissions 5-1 enhanced capabilities port see ecp enum# 3-14, 6-39, 19-2 error handling 11-1?11-12 exclusive access 12-1?12-2 f fifos 8-6, 8-7, 10-2, 11-3 fixed-priority scheme 13-2?13-3 flow-through 2-1, 8-6, 8-7, 17-1?17-3 primary 6-19, 17-1 secondary 6-26 gpio to package specs pci 6150bb data book, version 2.11 index-2 ? 2005 plx technology, inc. all rights reserved. g gpio 14-1 gpio[3:0] 3-3, 3-17, 4-1?4-4, 6-2, 6-32, 14-1 gpio3 3-3, 3-14, 3-17, 14-1, 19-1, 19-2 gpio3fn# 3-14, 19-1 gpioid register 6-32, 14-1 gpiood register 6-32, 14-1 gpiooe register 3-17, 6-32, 14-1 ground pins 3-19 h hardware 1-1, 3-11, 10-3, 21-1, 21-2 header registers 6-1, 6-3?6-16, 7-3 hot swap 3-1, 6-39, 19-1?19-2 pins 3-14 registers 3-14, 6-39, 19-1, 19-2 hs_cntl register 3-14, 6-39, 19-2 hs_csr register 3-14, 6-39, 19-2 hs_next register 3-14, 6-39, 19-2 i iacntrl register 6-27, 13-1, 13-2?13-3 ieee standard 1149.1-1990 21-1?21-2 ieee standard test access port and boundary-scan architecture see ieee standard 1149.1-1990 incremental prefetch count 6-24, 17-3 initialization 5-1?5-3 interface debug 21-1?21-2 gpio 14-1 high availability 19-1 jtag 21-1?21-2 primary 11-5, 15-1?15-2 secondary 11-5, 15-3 internal arbiter control register 6-2, 6-27, 13-1, 13-2? 13-3 isa 6-15, 7-3, 9-1, 9-4 j jtag 21-1?21-2 pins 3-3, 3-15 l lock 6-16, 12-1?12-2 m master abort see abort, master mechanical specs 22-1?22-6 memory prefetchable 6-12?6-13, 9-3 write and invalidate 6-4, 6-7, 6-22, 8-1, 8-2, 8-3, 8-12, 8-14, 10-1, 15-2, 15-3 miscellaneous options register 6-1, 6-21, 7-4, 8-3, 8-9, 11-1, 11-3 miscellaneous pins 3-17?3-18 mscopt register 6-21, 7-4, 8-3, 8-9, 10-2, 11-1, 11-3, 12-2 msk_in 3-2, 3-11, 4-1?4-2, 14-1 n normal termination vs. master abort 8-12, 8-13 o optimization basic design a-1 flow-through 17-1?17-3 ordering transactions 10-1?10-3 oscin 3-2, 3-11, 4-5, 5-1 oscsel# 3-2, 3-11, 4-5 p p_ad[31:0] 3-2, 3-4, 8-8, 8-9, 8-10 p_cbe[3:0]# 3-2, 3-4, 3-5, 8-2, 8-9, 15-1?15-2 p_clkin 3-2, 3-11, 4-1, 4-5, 5-1, 5-2, 19-1 p_devsel# 3-2, 3-4, 8-8, 11-1, 16-1, 16-2 p_frame# 3-2, 3-4, 6-7, 12-2 p_gnt# 3-2, 3-4, 13-1 p_idsel 3-2, 3-5, 8-8, 15-1 p_irdy# 3-2, 3-5, 6-19, 6-26 p_lock# 3-2, 3-5, 12-1?12-2 p_m66en 3-2, 3-5, 4-5, 5-1 p_par 3-2, 3-5, 13-1 p_perr# 3-2, 3-5, 6-5, 11-1?11-12 p_req# 3-2, 3-6, 13-1 p_rstin# 3-2, 3-13, 3-17, 4-1, 5-1?5-3, 7-1, 7-2, 14-1 p_serr# 3-2, 3-6, 6-2, 6-4, 6-5, 6-16, 6-31, 6-34, 8-4, 8-7, 8-8, 8-13, 8-14, 8-15, 8-16, 11-1?11-12, 12-2 p_stop# 3-2, 3-6 p_trdy# 3-2, 3-6 p_v io 3-3, 3-17 package specs 22-1?22-6 parity to pins pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. index-3 index parity 11-1?11-12 primary signal 3-5 reporting errors 16-2 secondary signal 3-8, 3-9 pbga mechanical specs 22-1, 22-5?22-6 package ordering information 1-5, b-1 pinout 22-6 pci 6150 general product information 1-1?1-6, b-2 ordering b-2 pci bus operation 8-1?8-18 pci bus power management interface specification, revision 1.1 see pci power mgmt. r1.1 pci configuration registers 6-1?6-41 pci local bus specification, revision 2.3 see pci r2.3 pci power mgmt. r1.1 2-1, 6-37, 18-1 pci r2.3 3-2, 5-1, 10-3, 20-1, 21-2 pci to pci bridge architecture specification, revision 1.1 see p-to-p bridge r1.1 pci transactions 8-1?8-18, 10-1?10-3 pci type 1 header registers 6-3?6-16 pcibistr register 6-7, 6-35, 7-3 pciccr register 6-6, 6-35 pciclsr register 6-7, 8-3, 17-2 pcicr register 6-4, 6-5, 6-10, 6-15, 6-16, 6-31, 7-3, 8-4, 8-7, 8-13, 8-14, 8-15, 8-16, 9-1, 9-2, 9-4, 9-5, 11-1? 11-12, 12-2, 16-2 pcihtr register 6-7, 6-35 pciidr register 6-3, 6-35, 7-3 pciiobar register 6-9, 6-15, 9-1, 9-2 pciiobaru16 register 6-9, 6-14, 9-1, 9-2 pciiolmt register 6-9, 9-1, 9-2 pciiolmtu16 register 6-9, 6-14, 9-1, 9-2 pciipr register 6-15 pciltr register 6-7 pcimbar register 6-11, 9-2, 9-3 pcimlmt register 6-11, 9-2, 9-3 pcipbno register 6-8, 8-11 pcipmbar register 6-12, 6-13, 9-2, 9-3 pcipmbaru32 register 6-12, 6-13, 9-2 pcipmlmt register 6-12, 6-13, 9-2, 9-3 pcipmlmtu32 register 6-12, 6-13, 9-2 pcirev register 6-6 pcisbno register 6-8, 8-9, 8-11 pcisltr register 6-8 pcisr register 3-17, 5-1, 6-5, 8-13, 8-14, 8-15, 8-16, 11-1?11-3, 11-5, 11-7, 11-12, 16-1 pcissr register 3-17, 5-1, 6-10, 8-13, 8-14, 8-15, 8-16, 11-1?11-3, 11-6, 11-8, 11-12, 16-1 pcisubno register 6-8, 8-11 pftcr register 6-19, 17-1 philips 74f166 4-2?4-4, 6-33 physical specs 22-1?22-6 picmg 2.1 r2.0 2-1, 19-1 picmg 2.1 r2.0 hot swap specification see picmg 2.1 r2.0 pin_led/eject 3-14, 19-2 pincpcnt register 6-24, 17-2, 17-3 pinout 3-4?3-19 pbga 22-6 pqfp 22-4 pins bpcc_en 3-3, 3-17, 6-38, 18-1 cfg66 3-3, 3-17, 5-1, 6-5, 6-10 clock related 3-2, 3-11 compactpci hot swap 3-3, 3-14 ee_en# 3-3, 3-16, 7-1, 7-2 eepclk 3-3, 3-16, 7-1 eepdata 3-3, 3-16, 7-1 eject_en# 3-14, 19-1, 19-2 enum# 3-14, 6-39, 19-2 gpio[3:0] 3-3, 3-17, 4-1?4-4, 6-2, 6-32, 14-1 gpio3 3-3, 3-14, 3-17, 14-1, 19-1, 19-2 gpio3fn# 3-14, 19-1 ground 3-19 hot swap 3-14 jtag 3-3, 3-15, 21-1 miscellaneous 3-17?3-18 msk_in 3-2, 3-11, 4-1?4-2, 14-1 oscin 3-2, 3-11, 4-5, 5-1 oscsel# 3-2, 3-11, 4-5 p_ad[31:0] 3-2, 3-4, 8-8, 8-9, 8-10 p_cbe[3:0]# 3-2, 3-4, 3-5, 8-2, 8-9, 15-1?15-2 p_clkin 3-2, 3-11, 4-1, 4-5, 5-1, 5-2, 19-1 p_devsel# 3-2, 3-4, 8-8, 11-1, 16-1, 16-2 p_frame# 3-2, 3-4, 6-7, 12-2 p_gnt# 3-2, 3-4, 13-1 p_idsel 3-2, 3-5, 8-8, 15-1 p_irdy# 3-2, 3-5, 6-19, 6-26 p_lock# 3-2, 3-5, 12-1?12-2 p_m66en 3-2, 3-5, 4-5, 5-1 p_par 3-2, 3-5, 13-1 p_perr# 3-2, 3-5, 6-5, 11-1?11-12 p_req# 3-2, 3-6, 13-1 p_rstin# 3-2, 3-13, 3-17, 4-1, 5-1?5-3, 7-1, 7-2, 14-1 p_serr# 3-2, 3-6, 6-2, 6-4, 6-5, 6-16, 6-31, 6-34, 8-4, 8-7, 8-8, 8-13, 8-14, 8-15, 8-16, 11-1?11-12, 12-2 pitlpcnt register to registers pci 6150bb data book, version 2.11 index-4 ? 2005 plx technology, inc. all rights reserved. p_stop# 3-2, 3-6 p_trdy# 3-2, 3-6 p_v io 3-3, 3-17 pin_led/eject 3-14, 19-2 power 3-19 primary clock 3-2 primary pci bus interface 3-2, 3-4?3-6 reserved 3-19 reset 3-2, 3-13, 5-1?5-3 s_ad[31:0] 3-2, 3-7, 3-13, 8-9, 8-10 s_cbe[3:0]# 3-2, 3-7, 3-8, 3-13, 5-2, 15-3 s_cfn# 3-3, 3-18, 13-1, 13-3 s_clkin 3-2, 3-11, 4-1, 4-2, 4-5, 5-2, a-1 s_clko[9:0] 3-2, 3-5, 3-8, 3-12, 4-1?4-5, 6-33, 6-38, a-1 s_devsel# 3-2, 3-7, 11-1, 16-1, 16-2 s_frame# 3-2, 3-7, 12-2, 13-2, 13-3 s_gnt[8:0]# 3-2, 5-2, 13-1 s_gnt[8:1]# 3-7, 3-8 s_gnt0# 3-7, 13-3 s_irdy# 3-2, 3-8, 13-3 s_lock# 3-2, 3-8, 12-1?12-2 s_m66en 3-2, 3-5, 3-8, 4-5, 5-1 s_par 3-2, 3-8, 3-13, 5-2, 13-3 s_perr# 3-2, 3-9, 6-10, 11-1?11-12 s_req[8:0]# 3-2, 6-18 s_req[8:1]# 3-2, 3-9 s_req0# 3-9, 13-3 s_rstout# 3-2, 3-11, 3-13, 4-1, 4-2, 5-1?5-3, 6-16, 6-18, 18-1 s_serr# 3-2, 3-6, 3-9, 6-15, 11-1?11-12 s_stop# 3-2, 3-9 s_trdy# 3-2, 3-10 s_v io 3-3, 3-18 secondary clock 3-2, 4-5 secondary pci bus interface 3-2, 3-7?3-10 serial eeprom 3-3, 3-16 tck 3-15, 21-1 tdi 3-15, 21-1, 21-2 tdo 3-15, 21-1, 21-2 tms 3-15, 21-1 trst# 3-15, 21-1, 21-2 v dd 3-1, 3-9, 3-16, 3-19, 23-1 v ss 3-19 see also pinout pitlpcnt register 6-23, 17-2 plx technology, inc. product information 1-1 product ordering and technical support b-2 pmaxpcnt register 6-25, 17-2, 17-3 pmc register 6-35, 6-36, 6-37, 7-4 pmcapid register 6-36 pmcdata register 6-35, 6-36, 6-38, 7-4 pmcsr register 5-2, 6-2, 6-35, 6-36, 6-38, 7-4, 18-1 pmcsr_bse register 6-38 pmnext register 6-36 power dissipation 1-2?1-3, 3-3, 4-1, 23-1 power management 18-1 capability registers 6-2, 6-36?6-38, 7-4 power pins 3-19 pqfp mechanical specs 22-1?22-4 package ordering information 1-5, b-1 pinout 22-4 prefetch 17-3 incremental count 6-24 memory 6-12?6-13, 9-3 read transaction 8-5?8-6 reprogramming registers 17-2 prefetch control registers 6-1, 6-23?6-25, 17-2 primary bus pins 3-2, 3-4?3-6 flow-through control register 6-1, 6-19 priority schemes 13-2?13-3 pserred register 6-31, 8-13?8-16, 11-1, 11-3 pserrsr register 6-34, 11-1 p-to-p bridge r1.1 9-3, 11-12 pull-up/pull-down resistor recommendations 3-2?3-3 pvpd_next register 2-1, 6-40 pvpdad register 2-1, 6-40 pvpdata register 2-1, 6-41 pvpdid register 2-1, 6-40 r read-only control register 6-2, 6-3, 6-6, 6-7, 6-35, 6-37, 6-38 registers acntrl 6-18, 6-27, 13-1 arbiter control 6-1, 6-18, 13-1 bcntrl 3-13, 4-2, 5-1, 5-2, 6-4, 6-15?6-16, 6-18, 6-20, 8-8, 9-1, 9-2, 9-4, 9-5, 11-1, 11-2, 11-3, 11-4, 11-5? 11-12 cap_ptr 6-5, 6-14 ccntrl 6-17, 8-5 chip control 6-1, 6-17, 8-5 control 6-2, 6-17?6-18, 6-20, 6-27, 6-33, 8-6 dcntrl 5-1, 5-2, 6-18 device-specific 6-17?6-41, 11-1, 11-3 diagnostic control 5-2, 6-1, 6-18 eepaddr 6-30, 7-1 eepcntrl 6-30, 7-1 eepdata 6-30, 7-1 gpioid 6-32, 14-1 gpiood 6-32, 14-1 gpiooe 3-17, 6-32, 14-1 reserved pin to s_req0# pci 6150bb data book, version 2.11 ? 2005 plx technology, inc. all rights reserved. index-5 index header 6-1, 6-3?6-16, 7-3 hot swap 3-14, 6-39, 19-1, 19-2 hs_cntl 3-14, 6-39, 19-2 hs_csr 3-14, 6-39, 19-2 hs_next 3-14, 6-39, 19-2 iacntrl 6-27, 13-1, 13-2?13-3 internal arbiter control 6-2, 6-27, 13-1, 13-2?13-3 miscellaneous options 6-1, 6-21, 7-4, 8-3, 11-1, 11-3 mscopt 6-21, 7-4, 8-3, 8-9, 10-2, 11-1, 11-3, 12-2 pci configuration 6-1?6-41 pci type 1 header 6-3?6-16 pcibistr 6-7, 6-35, 7-3 pciccr 6-6, 6-35 pciclsr 6-7, 8-3, 17-2 pcicr 6-4, 6-5, 6-10, 6-15, 6-16, 6-31, 7-3, 8-4, 8-7, 8-13, 8-14, 8-15, 8-16, 9-1, 9-2, 9-4, 9-5, 11-1?11-12, 12-2, 16-2 pcihtr 6-7, 6-35 pciidr 6-3, 6-35, 7-3 pciiobar 6-9, 6-15, 9-1, 9-2 pciiobaru16 6-9, 6-14, 9-1, 9-2 pciiolmt 6-9, 9-1, 9-2 pciiolmtu16 6-9, 6-14, 9-1, 9-2 pciipr 6-15 pciltr 6-7 pcimbar 6-11, 9-2, 9-3 pcimlmt 6-11, 9-2, 9-3 pcipbno 6-8, 8-11 pcipmbar 6-12, 6-13, 9-2, 9-3 pcipmbaru32 6-12, 6-13, 9-2 pcipmlmt 6-12, 6-13, 9-2, 9-3 pcipmlmtu32 6-12, 6-13, 9-2 pcirev 6-6 pcisbno 6-8, 8-9, 8-11 pcisltr 6-8 pcisr 3-17, 5-1, 6-5, 8-13, 8-14, 8-15, 8-16, 11-1?11-3, 11-5, 11-7, 11-12, 16-1 pcissr 3-17, 5-1, 6-10, 8-13, 8-14, 8-15, 8-16, 11-1? 11-3, 11-6, 11-8, 11-12, 16-1 pcisubno 6-8, 8-11 pftcr 6-19, 17-1 pincpcnt 6-24, 17-2, 17-3 pitlpcnt 6-23, 17-2 pmaxpcnt 6-25, 17-2, 17-3 pmc 6-35, 6-36, 6-37, 7-4 pmcapid 6-36 pmcdata 6-35, 6-36, 6-38, 7-4 pmcsr 5-2, 6-2, 6-35, 6-36, 6-38, 7-4, 18-1 pmcsr_bse 6-38 pmnext 6-36 power management capability 6-2, 6-36?6-38, 7-4, 18-1 prefetch control 6-23?6-25, 17-2 primary flow-through control 6-1, 6-19 pserred 6-31, 8-13?8-16, 11-1, 11-3 pserrsr 6-34, 11-1 pvpd_next 2-1, 6-40 pvpdad 2-1, 6-40 pvpdata 2-1, 6-41 pvpdid 2-1, 6-40 read-only control 6-2, 6-3, 6-6, 6-7, 6-35, 6-37, 6-38 rrc 6-2, 6-3, 6-6, 6-7, 6-35, 6-36, 6-37, 6-38 sclkcntrl 3-11, 4-1, 4-2, 4-3, 6-33 secondary flow-through control 6-26 serial eeprom 5-3, 6-29?6-30 sftcr 6-26, 17-1 sincpcnt 6-24, 17-2, 17-3 sitlpcnt 6-23, 17-2 smaxpcnt 6-25, 17-2, 17-3 system error event 6-31 test 6-29 timeout control 6-1, 6-20, 8-4 timer 6-16 tocntrl 6-20, 6-31, 8-4, 8-8 vpd 2-1, 6-40, 20-1 reserved pin 3-19 reset 5-1?5-3 jtag 21-1, 21-2 pins 3-2, 3-13, 5-1?5-3 resistor recommendations, pull-up/pull-down 3-2?3-3 rotating-priority scheme 13-2 rrc register 6-2, 6-3, 6-6, 6-7, 6-35, 6-36, 6-37, 6-38 rules, transaction ordering 10-1?10-3 s s_ad[31:0] 3-2, 3-7, 3-13, 8-9, 8-10 s_cbe[3:0]# 3-2, 3-7, 3-8, 3-13, 5-2, 15-3 s_cfn# 3-3, 3-18, 13-1, 13-3 s_clkin 3-2, 3-11, 4-1, 4-2, 4-5, 5-2, a-1 s_clko[9:0] 3-2, 3-5, 3-8, 3-12, 4-1?4-5, 6-33, 6-38, a-1 s_devsel# 3-2, 3-7, 11-1, 16-1, 16-2 s_frame# 3-2, 3-7, 12-2, 13-2, 13-3 s_gnt[8:0]# 3-2, 5-2, 13-1 s_gnt[8:1]# 3-7, 3-8 s_gnt0# 3-7, 13-3 s_irdy# 3-2, 3-8, 13-3 s_lock# 3-2, 3-8, 12-1?12-2 s_m66en 3-2, 3-5, 3-8, 4-5, 5-1 s_par 3-2, 3-8, 3-13, 5-2, 13-3 s_perr# 3-2, 3-9, 6-10, 11-1?11-12 s_req[8:0]# 3-2, 6-18 s_req[8:1]# 3-2, 3-9 s_req0# 3-9, 13-3 s_rstout# to v ss pci 6150bb data book, version 2.11 index-6 ? 2005 plx technology, inc. all rights reserved. s_rstout# 3-2, 3-11, 3-13, 4-1, 4-2, 5-1?5-3, 6-16, 6-18, 18-1 s_serr# 3-2, 3-6, 3-9, 6-15, 11-1?11-12 s_stop# 3-2, 3-9 s_trdy# 3-2, 3-10 s_v io 3-3, 3-18 sac 8-2, 9-3 sclkcntrl register 3-11, 4-1, 4-2, 4-3, 6-33 secondary bus pins 3-2, 3-7?3-10 clock pins 4-5 flow-through control register 6-26 serial eeprom 6-2, 7-1?7-3 pins 3-3, 3-16 registers 5-3, 6-29?6-30 sftcr register 6-26, 17-1 signal specs 22-1?22-6 sincpcnt register 6-24, 17-2, 17-3 single address cycle see sac sitlpcnt register 6-23, 17-2 smaxpcnt register 6-25, 17-2, 17-3 specs electrical 23-1?23-2 mechanical 22-1?22-6 spread spectrum clocking 5-1 system error event registers 6-31 t tap controller see test access port controller target abort see abort, target tck 3-15, 21-1 tdi 3-15, 21-1, 21-2 tdo 3-15, 21-1, 21-2 termination abnormal 12-2, 16-2 transaction 8-12?8-18 test access port controller 21-1, 21-2 test register 6-29 testability 21-1?21-2 timeout control 6-1 timeout control register 6-1, 6-20, 8-4 timer registers 6-16 tms 3-15, 21-1 tocntrl register 6-20, 6-31, 8-4, 8-8 transaction ordering rules 10-1?10-3 transaction termination 8-12?8-18 transactions, pci 8-1?8-18, 10-1?10-3 trst# 3-15, 21-1, 21-2 v v dd 3-1, 3-9, 3-16, 3-19, 23-1 vga 6-15, 9-1, 9-4, 9-4?9-5 vhdl 21-2 vhsic hardware description language 21-2 vpd registers 2-1, 6-40, 20-1 v ss 3-19 |
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